Browsing by Author "Tseng, Joshua"

6Å EOT Si0.45Ge0.55 pMOSFET with optimized reliability (VDD=1V): Meeting the NBTI lifetime target at ultra-thin EOT

8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution

Extending gate dielectric scaling by using ALD HfO2/SrTiO3 stacks

Extreme scaled gate dielectrics by using ALD Hf-based composite materials

Extreme scaled gate dielectrics by using ALD HfO2/SrTiO3 composite structures

Ge FETs gate stack passivation options and their scalability to low EOT

High hole mobility in 65 nm strained Ge p-channel field effect transistors with HfO2 gate dielectric

High hole-mobility 65nm biaxially-strained Ge-pFETs: fabrication, analysis and optimization

High-mobility 0.85nm-EOT Si0.45Ge0.55 pFETs: delivering high performance at scaled VDD

High-mobility Si1-xGex-channel PFETs: layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths

Implant-free SiGe qqantum well pFET: A novel, highly scalable and low thermal budget device, featuring raised source/drain and high-mobility channel.

On the origin of mobility reduction in ultrathin EOT HK/MG CMOS devices: Impact from gate-stack and device architecture

On the origin of the mobility reduction in bulk-Si, UTBOX-FDSOI and SiGe devices with ultrathin-EOT dielectrics

Optimized ultra-low thermal budget process flow for advanced high-K / metal gate first CMOS using laser-annealing technology

Oxygen incorporation in TiN for metal gate work function tuning with a replacement gate integration approach

Positive and negative bias temperature instability on sub-nanometer EOT high-K MOSFETs

Study of nitrogen impact on VFB-EOT roll-off by varying interfacial SiO2 thickness

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization