Browsing by Author "Veloso, Anabela"

1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor

2D and 3D Fully-depleted extension-less devices for advanced logic and memory applications

3D backside integration of FinFETs: Is there an impact on LF noise?

3D dopant profiling in silicon nanowires

3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors

45nm LSTP FET with FUSI gate on PVD-HfO2 with excellent drivability by advanced PDA treatment

A 50nm high-k poly silicon gate stack with a buried SiGe channel

A functional 41-stage ring oscillator using scaled FinFET devices with 25nm gate lengths and 10nm Fin widths applicable for the 45nm CMOS node

A new method to calculate leakage current and its applications for sub-45nm MOSFETs

A wafer-scaled III-V vertical FET fabrication by means of plasma etching

Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT

Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

Achieving Low-VT Ni-FUSI CMOS by ultra-thin Dy2O3 capping of hafnium silicate dielectrics

Achieving low-VT Ni-FUSI CMOS via Lanthanide incorporation in the gate stack

Active area patterning for CFET - Nanosheet etch

Addressing key concerns for implementation of Ni FUSI into manufacturing for 45/32 nm CMOS

Advanced CMOS device technologies for 45nm node and below

Advanced FinFET devices for sub-32nm technology nodes: characteristics and integration challenges

Advanced FinFET devices for sub-32nm technology nodes: characteristics and integration challenges

Advanced high voltage e-beam system combined with an enhanced D2DB for on-device overlay measurement