Browsing by Author "Verhaegen, Staf"

A 0.314mm2 6T-SRAM cell built with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

A methodology for double patterning compliant split and design

Analysis of the impact of reticle CD variations on the available process windows for a 100nm CMOS process

ArF lithography with combination of moderate OAI and attenuated PSM

Assessment of OPC effectiveness using two-dimensional metrics

CD control for two-dimensional features in future technology nodes

Challenge for sub-100-nm DRAM gate printing using ArF lithography with combination of moderate OAI and attPSM

Challenges building a 22nm node 6T-SRAM cell using immersion lithography

Challenges in patterning 45nm node multiple-gate devices and SRAM cells

Challenges in using optical lithography for the building of a 22 nm node 6T=-SRAM cell

Checking design conformance and optimizing manufacturability using automated double-patterning decomposition

Demonstration of scaled 0.099μm² FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

Density limits in logic metal1 using double patterning

Double patterning design split implementation and validation for the 32nm node

Double patterning EDA solutions for the 32nm HP and beyond

Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

EUV lithography implementation on contact and metal interconnect level of a 22nm node 0.099um2 6T-SRAM cell

Experimental verification of source-mask optimization and freeform illumination for 22 nm node SRAM cells

Exploration of etch step interactions in the dual patterning process for process modeling

Extreme scaling of optical lithography: overview of process integration issues