Browsing by Author "Zhou, Daisy"

Advanced channel materials for the semiconductor industry

An investigation on border traps in III-V MOSFETs with an In0.53Ga0.47As channel

Beyond-Si materials and devices for more Moore and more than Moore applications

Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs

Bias Temperature Instability (BTI) in high-mobility channel devices: SiGe, Ge, and InGaAs

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node

Buried power rail integration with FinFETs for ultimate CMOS scaling

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs

Demonstration of an InGaAs gate stack with sufficient PBTI reliability by thermal budget optimization, nitridation, high-k material choice, and interface dipole

Enabling CD SEM metrology for 5nm technology node and beyond

ESD characterization of planar InGaAs devices

FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral Circuits

Gate patterning development for monolithic CFET integration

Gate-all-around InGaAs nanowire FETs with peak transconductance of 2200 μS/μm at 50nm Lg using a replacement fin RMG flow

In0.53Ga0.47As quantum-well MOSFET with source-drain regrowth for low power logic applications

Reliability challenges of high mobility channel technologies: SiGe, Ge and InGaAs

Scalability of InGaAs nanowires demonstrating wire width down to 7nm and Lg down to 30nm fabricated on a 300mm Si platform

Scaled, novel effective workfunction metal gate stacks for advanced Low-VT, gate-all-around vertically stacked nanosheet FETs with reduced vertical distance between sheets