Browsing by author "Veloso, Anabela"

1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor

Lee, Jae Woo; Cho, Moon Ju; Simoen, Eddy; Ritzenthaler, Romain; Togo, Mitsuhiro; Boccardi, Guillaume; Mitard, Jerome; Ragnarsson, Lars-Ake; Chiarella, Thomas; Veloso, Anabela; Horiguchi, Naoto; Thean, Aaron; Groeseneken, Guido (2013-03)

2D and 3D Fully-depleted extension-less devices for advanced logic and memory applications

Veloso, Anabela; De Keersgieter, An; Aoulaiche, Marc; Jurczak, Gosia; Thean, Aaron; Horiguchi, Naoto (2012-09)

3D backside integration of FinFETs: Is there an impact on LF noise?

Simoen, Eddy; Jourdain, Anne; Claeys, Cor; Veloso, Anabela (2023)

3D dopant profiling in silicon nanowires

Fleischmann, Claudia; Melkonyan, Davit; Arnoldi, Laurent; Bogdanowicz, Janusz; Kumar, Arul; Veloso, Anabela; Vandervorst, Wilfried (2016)

3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors

Eyben, Pierre; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Veloso, Anabela; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Machillot, Jerome; Kim, Myungsun; Miyashita, Toshihiko; Yoshida, Naomi; Bender, Hugo; Richard, Olivier; Celano, Umberto; Paredis, Kristof; Wouters, Lennaert; Mitard, Jerome; Horiguchi, Naoto (2019)

45nm LSTP FET with FUSI gate on PVD-HfO2 with excellent drivability by advanced PDA treatment

Mitsuhashi, Riichirou; Yamamoto, Kazuhiko; Hayashi, S.; Rothschild, Aude; Kubicek, Stefan; Veloso, Anabela; Van Elshocht, Sven; Jurczak, Gosia; De Gendt, Stefan; Biesemans, Serge; Niwa, M. (2005)

A 50nm high-k poly silicon gate stack with a buried SiGe channel

Jakschik, S.; Hoffmann, Thomas Y.; Cho, Hag-Ju; Veloso, Anabela; Loo, Roger; Hyun, S.; Sorada, H.; Inoue, A.; de Potter de ten Broeck, Muriel; Eneman, Geert; Severi, Simone; Absil, Philippe; Biesemans, Serge (2007)

A functional 41-stage ring oscillator using scaled FinFET devices with 25nm gate lengths and 10nm Fin widths applicable for the 45nm CMOS node

Collaert, Nadine; Dixit, Abhisek; Goodwin, Michael; Kottantharayil, Anil; Rooyackers, Rita; Degroote, Bart; Leunissen, Peter; Veloso, Anabela; Jonckheere, Rik; De Meyer, Kristin; Jurczak, Gosia; Biesemans, Serge (2004-08)

A new method to calculate leakage current and its applications for sub-45nm MOSFETs

Lujan, Guilherme; Magnus, Wim; Soree, Bart; Pourghaderi, Mohammad Ali; Veloso, Anabela; Van Dal, Mark; Lauwers, Anne; Kubicek, Stefan; De Gendt, Stefan; Heyns, Marc; De Meyer, Kristin (2005)

A wafer-scaled III-V vertical FET fabrication by means of plasma etching

Milenin, Alexey; Veloso, Anabela; Collaert, Nadine; Piumi, Daniele (2018)

Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT

Rothschild, Aude; Shi, Xiaoping; Everaert, Jean-Luc; Kerner, Christoph; Chiarella, Thomas; Hoffmann, Thomas; Vrancken, Christa; Shickova, Adelina; Yoshinao, H.; Mitsuhashi, Riichirou; Niwa, Masaaki; Lauwers, Anne; Veloso, Anabela; Kittl, Jorge; Absil, Philippe; Biesemans, Serge (2007)

Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

Veloso, Anabela; Yu, HongYu; Lauwers, Anne; Chang, Shou-Zen; Adelmann, Christoph; Onsia, Bart; Demand, Marc; Brus, Stephan; Vrancken, Christa; Singanamalla, Raghunath; Lehnen, Peer; Kittl, Jorge; Kauerauf, Thomas; Vos, Rita; O'Sullivan, Barry; Van Elshocht, Sven; Mitsuhashi, Riichirou; Whittemore, G.; Yin, K.M.; Niwa, Masaaki; Hoffmann, Thomas; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2007-09)

Achieving Low-VT Ni-FUSI CMOS by ultra-thin Dy2O3 capping of hafnium silicate dielectrics

Veloso, Anabela; Yu, HongYu; Chang, S.Z.; Adelmann, Chris; Onsia, Bart; Brus, Stephan (2007)

Achieving low-VT Ni-FUSI CMOS via Lanthanide incorporation in the gate stack

Veloso, Anabela; Yu, HongYu; Lauwers, Anne; Chang, Shou-Zen; Adelmann, Christoph; Onsia, Bart; Demand, Marc; Brus, Stephan; Vrancken, Christa; Singanamalla, Raghunath; Lehnen, Peer; Kittl, Jorge; Kauerauf, Thomas; Vos, Rita; O'Sullivan, Barry; Van Elshocht, Sven; Mitsuhashi, Riichirou; Whittemore, G.; Yin, K.M.; Niwa, Masaaki; Hoffmann, Thomas; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2008)

Active area patterning for CFET - Nanosheet etch

Brissonneau, Vincent; Koo, Il Gyo; Hosseini, Maryam; Batuk, Dmitry; Veloso, Anabela; Mannaert, Geert; Lazzarino, Frederic (2024)

Addressing key concerns for implementation of Ni FUSI into manufacturing for 45/32 nm CMOS

Shickova, Adelina; Kauerauf, Thomas; Rothschild, Aude; Aoulaiche, Marc; Sahhaf, Sahar; Kaczer, Ben; Veloso, Anabela; Torregiani, Cristina; Pantisano, Luigi; Lauwers, Anne; Zahid, Mohammed; Rost, Tim; Tigelaar, H.; Pas, M.; Fretwell, J.; McCormack, J.; Hoffmann, Thomas; Kerner, Christoph; Chiarella, Thomas; Brus, Stephan; Harada, Yoshinao; Niwa, Masaaki; Kaushik, Vidya; Maes, Herman; Absil, Philippe; Groeseneken, Guido; Biesemans, Serge; Kittl, Jorge (2007)