Browsing by author "De Keersgieter, An"
Now showing items 1-20 of 143
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25% drive current improvement for p-type Multiple Gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions
Verheyen, Peter; Collaert, Nadine; Rooyackers, Rita; Loo, Roger; Shamiryan, Denis; De Keersgieter, An; Eneman, Geert; Leys, Frederik; Dixit, Abhisek; Goodwin, Michael; Yim, Yong Sik; Caymax, Matty; De Meyer, Kristin; Absil, Philippe; Jurczak, Gosia; Biesemans, Serge (2005) -
2D and 3D Fully-depleted extension-less devices for advanced logic and memory applications
Veloso, Anabela; De Keersgieter, An; Aoulaiche, Marc; Jurczak, Gosia; Thean, Aaron; Horiguchi, Naoto (2012-09) -
3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors
Eyben, Pierre; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Veloso, Anabela; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Machillot, Jerome; Kim, Myungsun; Miyashita, Toshihiko; Yoshida, Naomi; Bender, Hugo; Richard, Olivier; Celano, Umberto; Paredis, Kristof; Wouters, Lennaert; Mitard, Jerome; Horiguchi, Naoto (2019) -
3D-carrier profiling in FinFETs using scanning spreading resistance microscopy
Mody, Jay; Zschaetzsch, Gerd; Koelling, Sebastian; De Keersgieter, An; Eneman, Geert; Kambham, Ajay Kumar; Drijbooms, Chris; Schulze, Andreas; Chiarella, Thomas; Horiguchi, Naoto; Hoffmann, Thomas; Eyben, Pierre; Vandervorst, Wilfried (2011) -
A comparative study of the oxide breakdown in short-channel nMOSFETs and pMOSFETs stressed in inversion and in accumulation regimes
Crupi, F.; Kaczer, Ben; Degraeve, Robin; De Keersgieter, An; Groeseneken, Guido (2003) -
A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions
Sasaki, Yuichiro; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Kubicek, Stefan; Rosseel, Erik; Waite, Andrew; del Agua Borniquel, Jose Ignacio; Colombeau, Benjamin; Chew, Soon Aik; Kim, Min-Soo; Schram, Tom; Demuynck, Steven; Vandervorst, Wilfried; Horiguchi, Naoto; Mocuta, Dan; Mocuta, Anda; Thean, Aaron (2015-06) -
A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C
Collaert, Nadine; Aoulaiche, Marc; De Wachter, Bart; Rakowski, Michal; Redolfi, Augusto; Brus, Stephan; De Keersgieter, An; Horiguchi, Naoto; Altimime, Laith; Jurczak, Gosia (2010) -
A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 10^16 endurance at 85°C
Lu, Zhichao; Collaert, Nadine; Aoulaiche, Marc; De Wachter, Bart; De Keersgieter, An; Schwarzenbach, W.; Bonnin, O.; Bourdelle, K.K.; Nguyen, B.-Y.; Mazure, C.; Altimime, Laith; Jurczak, Gosia (2010) -
A simulation evaluation of 100 nm CMOS device performance
Jones, S. K.; Bazley, D. J.; Augendre, Emmanuel; Badenes, Gonçal; De Keersgieter, An; Skotnicki, T. (2001) -
Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations
Eyben, Pierre; Matagne, Philippe; Chiarella, Thomas; De Keersgieter, An; Kubicek, Stefan; Mitard, Jerome; Mocuta, Anda; Horiguchi, Naoto; Thean, Aaron; Mocuta, Dan (2016) -
Advanced 2D/3D simulations for laser annealed device using an atomic kinetic monte carlo approach and scanning spreading resistance microscopy (SRRM)
Noda, T.; Eyben, Pierre; Vandervorst, Wilfried; Vrancken, Christa; Rosseel, Erik; Ortolland, Claude; Clarysse, Trudo; Goossens, Jozefien; De Keersgieter, An; Felch, S.; Schreutelkamp, Rob; Absil, Philippe; Jurczak, Gosia; De Meyer, Kristin; Biesemans, Serge; Hoffmann, Thomas Y. (2008) -
Advanced FinFET devices for sub-32nm technology nodes: characteristics and integration challenges
Veloso, Anabela; Collaert, Nadine; De Keersgieter, An; Witters, Liesbeth; Rooyackers, Rita; Van Dal, Mark; Duffy, Ray; Pawlak, Bartek; Lander, Rob; Hoffmann, Thomas Y. (2009) -
Advanced FinFET devices for sub-32nm technology nodes: characteristics and integration challenges
Veloso, Anabela; Collaert, Nadine; De Keersgieter, An; Witters, Liesbeth; Rooyackers, Rita; Hoffmann, Thomas; Biesemans, Serge; Jurczak, Gosia (2009) -
Advances on doping strategies for triple-gate FinFETs and lateral gate-all-around nanowire FETs and their impact on device performance
Veloso, Anabela; De Keersgieter, An; Matagne, Philippe; Horiguchi, Naoto; Collaert, Nadine (2017) -
Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET
Arimura, Hiroaki; Eneman, Geert; Capogreco, Elena; Witters, Liesbeth; De Keersgieter, An; Favia, Paola; Porret, Clément; Hikavyy, Andriy; Loo, Roger; Bender, Hugo; Ragnarsson, Lars-Ake; Mitard, Jerome; Collaert, Nadine; Mocuta, Dan; Horiguchi, Naoto (2018) -
Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study
Kaczer, Ben; Degraeve, Robin; Rasras, Mahmoud; De Keersgieter, An; Van de Mieroop, Koen; Groeseneken, Guido (2002) -
Analysis and optimisation of the 2D-dopant profile in a 90 nm CMOS technology using scanning spreading resistance microscopy
Eyben, Pierre; Alvarez, David; Jurczak, Gosia; Rooyackers, Rita; De Keersgieter, An; Augendre, Emmanuel; Vandervorst, Wilfried (2003) -
Analysis of diffusion mechanisms for SSD in confined volumes : An alternative solution for extension formation in N7 and N5 technologies
Eyben, Pierre; Pawlak, Bartek; De Keersgieter, An; Kikuchi, Yoshiaki; Mitard, Jerome; Horiguchi, Naoto; Mocuta, Dan; Mocuta, Anda (2018) -
Analysis of the two-dimensional-dopant profile in a 90 nm complementary metal-oxide-semiconductor technology using scanning spreading resistance microscopy
Eyben, Pierre; Alvarez, David; Jurczak, Gosia; Rooyackers, Rita; De Keersgieter, An; Augendre, Emmanuel; Vandervorst, Wilfried (2004-01) -
Arsenic and phosphorus co-implantation for deep-submicron CMOS gate and source/drain engineering
Augendre, Emmanuel; De Keersgieter, An; Kubicek, Stefan; Redolfi, Augusto; Van Laer, Joris; Badenes, Gonçal (2001)