Browsing by Author "Cho, Moon Ju"

1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor

6Å EOT Si0.45Ge0.55 pMOSFET with optimized reliability (VDD=1V): Meeting the NBTI lifetime target at ultra-thin EOT

8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

A consistent model for oxide trap profiling with the trap spectroscopy by charge injection and sensing (TSCIS) technique

A low-power HKMG CMOS platform compatible with DRAM node 2x and beyond

A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies

Abrupt breakdown in dielectric/metal gate stacks: a potential reliability limitation?

Advanced doping techniques for DRAM peripheral MOSFETs

Advanced PBTI reliability with 0.69nm EOT GdHfO gate dielectric

Al-induced defect generation in cubic phase HfO2/SiO2/Si gate stacks

Analysis of the interface trap density in SOI FinFETs with different TiN gate electrode thickness through charge pumping technique

Atomic layer deposition process of Hf-based high-k gate dielectric film on Si substrate

Bias-temperature instability of Si and Si(Ge)-channel sub-1nm EOT p-MOS devices: challenges and solutions

BTI reliability of advanced gate stacks for beyond silicon devices: challenges and opportunities

BTI reliability of high-mobility channel devices: SiGe, Ge and InGaAs

Channel hot carrier degradation and self-heating effects in FinFETs

Channel hot carrier degradation mechanism in long/short channel n-FinFETs

Characterizing oxide traps in the InGaAs/Al2O3 system with sulfur passivation

Comparison of NBTI aging on adder architectures and ring oscillators in the downscaled technologies

Defect profiling in the SiO2/Al2O3 interface using variable Tcharge-Tdischarge amplitude charge pumping (VT2ACP)