Browsing by Author "Demand, Marc"
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Publication 45nm nMOSFET with metal gate on thin SiON driving 1150μA/μm and off-state of 10nA/μm
; ; Publication A 35nm diameter vertical silicon nanowire short-gate tunnelFET
Proceedings paper2009, Nanotechnology Workshop, 13/06/2009Publication A fully planar stacked gate flash technology with T-shaped floating gate for increased cell coupling ratio
; ; ; ; ; Proceedings paper2007, Proceedings 2nd International Conference on Memory Technology and Design - ICMTD, 7/05/2007, p.243-245Publication A new complementary hetero-junction vertical tunnel-FET integration scheme
Proceedings paper2013, International Electron Devices Meeting - IEDM, 9/12/2013, p.92-95Publication Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack
Proceedings paper2007-09, Proceedings of the 37th European Solid-State Device Research Conference - ESSDERC, 11/09/2007Publication Achieving low-VT Ni-FUSI CMOS via Lanthanide incorporation in the gate stack
Journal article2008, Solid-State Electronics, (52) 9, p.1303-1311Publication Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs
Journal article2013, Solid-State Electronics, 83, p.50-55Publication Approaches to Enable Patterning of Tight Pitches towards High NA EUV
Publication Capping-metal gate integration technology for multiple-VT CMOS in MuGFETs
Proceedings paper2008, IEEE International SOI Conference Proceedings, 6/10/2008, p.119-120Publication Challenges building a 22nm node 6T-SRAM cell using immersion lithography
Proceedings paper2009, 6th International Symposium on Immersion Lithography Extensions, 22/10/2009Publication Challenges in using optical lithography for the building of a 22 nm node 6T=-SRAM cell
Journal article2010, Microelectronic Engineering, (87) 5_8, p.993-996Publication Cost effective low Vt Ni-FUSI CMOS on SiON by means of Al implant (pMOS) and Yb+P implant (nMOS)
Journal article2008, IEEE Electron Device Letters, (29) 1, p.34-37Publication Demonstration of recessed SiGe S/D and inserted metal gate on HfO2 for high performance pFETs
Proceedings paper2005-12, Technical Digest International Electron Devices Meeting (IEDM), 5/12/2005, p.907-910Publication Demonstration of scaled 0.099μm² FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology
Proceedings paper2009-12, IEEE International Electron Devices Meeting - IEDM, 7/12/2009, p.301-304Publication Development of AlGaN recess etch for Emode POWER HEMTs
Meeting abstract2012, Plasma Etch and Strip in Microelectronics - PESM, 15/03/2012Publication Direct SiGe BFFT patterning by dry plasma etching
Meeting abstract2012, ECS Fall Meeting Symposium E13: Plasma Processing 19, 7/10/2012, p.2922Publication Discovering practical use of sensor wafers in CCP reactors
Proceedings paper2011, China Semiconductor Technology International Conference - CSTIC, 13/03/2011, p.409-414Publication Double hard mask strategy for patterning 0.186 micron2 SRAM cells using FinFET technology
Proceedings paper2008, 30th Dry Process Symposium, 26/11/2008, p.23-24Publication Dry etch of Yb-doped poly-Si gates for low Vt FUSI devices
Proceedings paper2007, Plasma Etch and Strip in Microelectronics, 10/09/2007Publication Dry etch processing of Multiple Gate FETs with metal gate electrode
Proceedings paper2005, Dry Process Symposium, 28/11/2005