Browsing by Author "Dixit, Abhisek"

25% drive current improvement for p-type Multiple Gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions

A 0.314mm2 6T-SRAM cell built with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

A functional 41-stage ring oscillator using scaled FinFET devices with 25nm gate lengths and 10nm Fin widths applicable for the 45nm CMOS node

A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM

Accurate fin patterning in emerging devices for 32nm and beyond

Analysis of the parasitic S/D resistance in multiple-gate FETs

Characterization and modeling of hot carrier degradation in N-channel gate-all-around nanowire FETs

Characterization and modeling of N-channel bulk FinFETs from DC to high frequency

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

Cryogenic temperature DC-IV measurements and compact modeling of n-channel bulk FinFETs with 3-4 nm wide fins and 20 nm gate length for quantum computing applications

Doubling or quadrupling MuGFET Fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

FEOL CMOS process- and device-parasitics in SOI-MuGFETs

FinFET analogue characterization from DC to 110 GHz

Geometry dependence of low frequency noise in n- and p- channel MuGFETs

GIDL (gate-induced drain leakage) and parasitic Schottky barrier leakage elimination in aggressively scaled HfO2/TiN FiNFET devices

Impact of LER and random dopant fluctuations on FinFET matching performance

Impact of line-edge roughness on FinFET matching performance

Integration challenges for multi-gate devices

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274μm² 6T-SRAM cell and advanced CMOS logic circuits

Measurement and analysis of parasitic capacitance in FinFETs with high-k dielectrics and metal-gate stack