Browsing by Author "Horiguchi, Naoto"
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Publication 1.5×10-9 Ω·cm² Contact Resistivity on Highly Doped Si:P Using Ge Pre-amorphization and Ti Silicidation
Proceedings paper2015, IEEE International Electron Devices Meeting - IEDM, 7/12/2015, p.592-595Publication 1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor
Journal article2013-03, Applied Physics Letters, (102) 7, p.73503Publication 15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process
Proceedings paper2014, Symposium on VLSI Technology, 9/06/2014, p.138-139Publication 1mA/μm-ION strained SiGe45%-IFQW pFETs with raised and embedded S/D
; ; ; ; Proceedings paper2011, Symposium on VLSI Technology, 13/06/2011, p.134-135Publication 2D and 3D Fully-depleted extension-less devices for advanced logic and memory applications
Proceedings paper2012-09, International Conference on Solid State Devices and Materials - SSDM, 25/09/2012Publication 3D sequential CMOS top tier devices demonstration using a low temperature Smart Cu (TM) Si layer transfer
Proceedings paper2021, 26th Silicon Nanoelectronics Workshop, JUN 13, 2021, p.47-48Publication 3D sequential low temperature top tier devices using dopant activation with excimer laser anneal and strained silicon as performance boosters
Proceedings paper2020, IEEE Symposium on VLSI Technology and Circuits, JUN 15-19, 2020Publication 3D simulation for melt laser anneal integration in FinFET's contact
Publication 3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors
Proceedings paper2019, IEEE International Electron Devices Meeting - IEDM 2019, 7/12/2019, p.238-241Publication 3D-carrier profiling in FinFETs using scanning spreading resistance microscopy
Proceedings paper2011, IEEE International Electron Devices Meeting - IEDM, 5/12/2011, p.119-122Publication 80 nm tall thermally stable cost effective FinFETs for advanced dynamic random access memory periphery devices for artificial intelligence/machine learning and automotive applications
Journal article2021, JAPANESE JOURNAL OF APPLIED PHYSICS, (60) SB, p.SBBB06Publication 80nm tall thermally stable cost effective FinFETs for advanced DRAM periphery devices for AI/ML and Automotive applications
Proceedings paper2020, 2020 International Conferene on Solid State Devices and Materials - SSDM, 27/09/2020, p.B-10-03Publication 85nm-wide 1.5mA/μm-ION IFQW SiGe-pFET: raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study
Proceedings paper2012, Symposium on VLSI Technology - VLSIT, 12/06/2012, p.163-164Publication A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs
Proceedings paper2016-06, IEEE Symposium on VLSI Technology, 13/06/2016, p.34-35Publication A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions
Proceedings paper2015-06, IEEE Symposium on VLSI Technology, 15/06/2015, p.30-31Publication A DRAM compatible Cu contact using self-aligned Ta-silicide and Ta-barrier
Journal article2008, Microelectronic Engineering, (85) 10, p.2009-2012Publication A low-power HKMG CMOS platform compatible with DRAM node 2x and beyond
Journal article2014, IEEE Transactions on Electron Devices, (61) 8, p.2935-2943Publication A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.161-162Publication A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies
Proceedings paper2014, International Electron Devices Meeting - IEDM, 15/12/2014, p.772-775