Browsing by Author "Oniki, Yusuke"

At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells

Challenges and solutions of replacement metal gate patterning to enable gate-all-around device scaling

Cleaning challenges associated with scaling boosters and performance enhancement for advanced logic devices

Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond

Controlled isotropic etches for Gate-All-Around (GAA) device architectures

Development of Metal Free Wet Etching Chemical for Ruthenium Interconnect

Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices

Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond

Dry removal of a surface functionalization chemistry used for pattern collapse prevention

Enabling CMOS scaling towards 3nm and beyond

Enabling complimentary FET (CFET) fabrication: selective, isotropic etch of Group IV semiconductors

Enhanced light coupling into nanostructured arrays as an enabler for advanced Raman-based metrology

FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral Circuits

First demonstration of ruthenium and molybdenum word lines integrated into 40nm ptch 3D NAND memory devices

First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP

Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space

Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures

Functional water solutions to enable advanced wet cleaning process for next generation semiconductor device manufacturing

Functional water solutions to enable wet cleaning process for leading edge semiconductor device manufacturing

Insights into Scaled Logic Devices Connected from Both Wafer Sides