Browsing by Author "Santoro, Gaetano"

3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors

Characterizing immersion lithography micro bridge defects using advanced features of teh SEMVision G3 STAR FIB

CMP of a RU based layer in an advanced Cu low-k stack

Direct yield prediction from SEM images

e-beam metrology of thin resist for high NA EUVL

Enabling Non-Actinic EUV Mask Inspection using CNT Pellicle

EUV mask defectivity study by existing DUV tools and new EBEAM technology

Metrology of Thin Resist for High NA EUVL

Micro-bridge defects: characterization and root cause analysis

Post-direct-CMP dielectric surface copper contamination: quantitative analysis and impact on dielectric breakdown behaviour

Post-direct-CMP dielectric surface copper contamination: quantitative analysis and impact on dielectric breakdown behaviour

Recess metrology challenges for 3D device architectures in advanced technology nodes

Scaled, novel effective workfunction metal gate stacks for advanced Low-VT, gate-all-around vertically stacked nanosheet FETs with reduced vertical distance between sheets

Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced nanowires separation, new work function metal gate solutions, and DC/AC performance optimization

Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration