Browsing by Author "Tan, Chi Lim"
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Publication 15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU
Proceedings paper2013, Advanced Etch Technology for Nanopatterning II, 23/02/2013, p.86850CPublication 3D measurement of 3D NAND memory hole with CD-SEM and tilted FIB
Publication Analysis of performance/variability trade-off in Macaroni-type 3-D NAND Memory
Proceedings paper2014, IEEE 6th International Memory Workshop, 18/05/2014, p.123-126Publication Enabling CD SEM metrology for 5nm technology node and beyond
Proceedings paper2017, Metrology, Inspection, and Process Control for Microlithography XXXI, 26/02/2017, p.1014512Publication Experimental and theoretical verification of channel conductivity degradation due to grain boundaries and defects in 3D NAND
Proceedings paper2017, IEEE International Electron Devices Meeting - IEDM, 2/12/2017, p.517-520Publication Experimental study of programming saturation in low-coupling planar high-k/metal gate Nand flash memory cells using a dedicated test structure
Proceedings paper2014, IEEE 6th International Memory Workshop - IMW, 18/05/2014, p.1-4Publication Feasibility of InxGa1-xAs high mobility channel for 3-D NAND memory
Journal article2017, IEEE Transactions on Electron Devices, (64) 1, p.130-136Publication In depth analysis of 3D NAND enablers in gate stack integration and demonstration in 3D devices
Proceedings paper2017, International Memory Workshop, 14/05/2017, p.1-4Publication Integration of a multi-layer inter-gate dielectric with hybrid floating gate towards 10nm planar NAND flash
Proceedings paper2014, 6th International Memory Workshop, 18/05/2014, p.51-54Publication Intergate dielectric engineering towards large P/E window planar NAND flash
; ; ; Journal article2015, IEEE Transactions on Electron Devices, (62) 5, p.1484-1490Publication Junctionless array with ultrathin poly\TiN floating gate and HfAlO based intergate dielectric for sub-15nm planar NAND Flash
; ; ; ; ; Proceedings paper2016-05, International Memory Workshop - IMW, 15/05/2016, p.113-116Publication Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning
Journal article2013-09, Journal of Micro/Nanolithography MEMS and MOEMS, (12) 4, p.41302Publication Laser thermal anneal of polysilicon channel to boost 3D memory performance
Proceedings paper2014, Symposium on VLSI Technology, 9/04/2014, p.24-25Publication MOVPE In1-xGaxAs high mobility channel for 3-D NAND memory
Proceedings paper2015, International Electron Devices Meeting - IEDM, 7/12/2015, p.40-43Publication Passivation of poly-Si channel vertical NAND devices du high pressure annealing
Proceedings paper2016-05, International Memory Workshop - IMW, 15/05/2016, p.88-91Publication Precise measurement of thin film thickness in 3D-NAND device with CD-SEM
Publication Precise measurement of thin-film thickness in 3D-NAND device with CD-SEM
Journal article2018, Journal of Micro/Nanolithography MEMS and MOEMS, (17) 2, p.24002Publication SiGe channel formation for 3D vertical channel transistor applications
Meeting abstract2014, E-MRS Fall Meeting J: Alternative Integration in Si Microelectronics, 15/09/2014, p.6 2Publication Stacked-etch induced charge loss in hybrid floating gate cells using high- $j inter-gate dielectric
Proceedings paper2014, International Reliability Physics Symposium - IRPS, 1/06/2014, p.MY-1.1-MY-1.5Publication Statistical spectroscopy of switching traps in deeply scaled vertical poly-Si channel for 3D memories
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