Browsing by author "Gonzalez, Mario"
Now showing items 1-20 of 209
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3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps
Guo, Wei; Van der Plas, Geert; Ivankovic, Andrej; Eneman, Geert; Cherman, Vladimir; De Wachter, Bart; Mercha, Abdelkarim; Gonzalez, Mario; Civale, Yann; Redolfi, Augusto; Buisson, Thibault; Jourdain, Anne; Vandevelde, Bart; Rebibis, Kenneth June; De Wolf, Ingrid; La Manna, Antonio; Beyer, Gerald; Beyne, Eric; Swinnen, Bart (2012) -
3D stacking induced mechanical stress effects
Cherman, Vladimir; Van der Plas, Geert; De Vos, Joeri; Ivankovic, Andrej; Lofrano, Melina; Simons, Veerle; Gonzalez, Mario; Vanstreels, Kris; Wang, Teng; Daily, Robert; Guo, Wei; Beyer, Gerald; La Manna, Antonio; De Wolf, Ingrid; Beyne, Eric (2014) -
A methodology for mechanical stress and wafer warpage minimization during 3D NAND fabrication
Kruv, Anastasiia; Gonzalez, Mario; Okudur, Oguzhan Orkut; Spampinato, Valentina; Franquet, Alexis; Vadakupudhu Palayam, Senthil; Arreghini, Antonio; Van den Bosch, Geert; Rosmeulen, Maarten; De Wolf, Ingrid (2022) -
A multilevel sub-modeling approach to evaluate 3D IC packaging induced stress on hybrid interconnect structures
Lofrano, Melina; Gonzalez, Mario; Vandevelde, Bart (2014) -
A multilevel sub-modeling approach to evaluate 3D IC packaging induced stress on hybrid interconnect structures
Lofrano, Melina; Gonzalez, Mario; Vandevelde, Bart; Tokei, Zsolt (2013) -
A novel concept for advanced modules with back-contact solar cells
Govaerts, Jonathan; Robbelein, Jo; Gong, Chun; Pawlak, Bartek; Gonzalez, Mario; De Wolf, Ingrid; Bossuyt, Frederick; Van Put, Steven; Gordon, Ivan; Vanfleteren, Jan; Beaucarne, Guy; van der Heide, Arvid; Dewallef, Stefan; Baert, Kris (2010-10) -
A novel fan-out concept for ultra-high chip-to-chip interconnect density with 20-μm pitch
Podpod, Arnita; Slabbekoorn, John; Phommahaxay, Alain; Duval, Fabrice; Salahouelhadj, Abdellah; Gonzalez, Mario; Rebibis, Kenneth June; Miller, Andy; Beyer, Gerald; Beyne, Eric (2018) -
A novel interconnect design with high stretchability and fine pitch capability for applications in stretchable electronics
Hsu, Yung-Yu; Gonzalez, Mario; Bossuyt, Frederick; Axisa, Fabrice; Vanfleteren, Jan; De Wolf, Ingrid (2009) -
A numerical study on nano-indentation induced fracture of low dielectric constant brittle thin films using cube corner probes
Zahedmanesh, Houman; Vanstreels, Kris; Gonzalez, Mario (2016) -
A Study of SiCN Wafer-to-Wafer Bonding and Impact of Wafer Warpage
Iacovo, Serena; D'have, Koen; Okudur, Oguzhan Orkut; De Vos, Joeri; Uhrmann, Thomas; Plach, Thomas; Conard, Thierry; Meersschaut, Johan; Bex, Pieter; Brems, Steven; Phommahaxay, Alain; Gonzalez, Mario; Witters, Liesbeth; Beyer, Gerald; Beyne, Eric (2023) -
Advanced experimental Back-End-Of-Line (BEOL) stability test: measurements and simulations
Vanstreels, Kris; Cherman, Vladimir; Gonzalez, Mario; De Wolf, Ingrid; Van der Plas, Geert; De Vos, Joeri; Boemmels, Juergen; Tokei, Zsolt (2015) -
Advanced experimental BEOL stability test: measurements and simulations
Vanstreels, Kris; Cherman, Vladimir; Gonzalez, Mario; De Wolf, Ingrid; Van der Plas, Geert; De Vos, Joeri; Boemmels, Juergen; Tokei, Zsolt (2014) -
Alternative Cu pillar bumps design to reduce thermomechanical stress induced during flip chip assembly
Lofrano, Melina; Cherman, Vladimir; Gonzalez, Mario; Beyne, Eric (2017) -
An analysis of the reliability of a wafer level package (WLP) using a silicon under the bump (SUB) configuration
Gonzalez, Mario; Vandevelde, Bart; Vanden Bulcke, Mathieu; Winters, Christophe; Beyne, Eric; Lee, Y.J.; Harkness, B.R.; Mohamed, M.; Meynen, H.; Vanlathem, E. (2003) -
An efficient bump pad design to mitigate the flip chip package induced stress
Gonzalez, Mario; De Vos, Joeri; Van der Plas, Geert; Beyne, Eric (2015) -
An investigation of thermo-mechanical stress in IC's induced during chip assembly
Lofrano, Melina; Gonzalez, Mario; Cherman, Vladimir; Beyne, Eric (2018) -
Analysis of copper plasticity impact in TSV-middle and backside TSV-last fabrication processes
Guo, Wei; Karmarkar, Aditya; Xu, Xiaopeng; Van der Plas, Geert; Van Huylenbroeck, Stefaan; Gonzalez, Mario; Absil, Philippe; El Sayed, Karim; Beyne, Eric (2015) -
Analysis of microbump induced stress effects in 3D stacked IC technologies
Ivankovic, Andrej; Van der Plas, Geert; Moroz, V.; Choi, M.; Cherman, Vladimir; Mercha, Abdelkarim; Marchal, Pol; Gonzalez, Mario; Eneman, Geert; Zhang, Wenqi; Buisson, Thibault; Detalle, Mikael; La Manna, Antonio; Verkest, Diederik; Beyer, Gerald; Beyne, Eric; Vandevelde, Bart; De Wolf, Ingrid; Vandepitte, Dirk (2012) -
Analysis of the induced stresses in silicon during thermocompression Cu-Cu bonding of Cu-through-vias in 3D-SIC architecture
Okoro, Chukwudi; Eneman, Geert; Gonzalez, Mario; Vandevelde, Bart; Swinnen, Bart; Stoukatch, Serguei; Beyne, Eric; Vandepitte, Dirk (2007-05) -
Analysis of the mechanical integrity of nano-interconnects; A novel approach inspired by composite mechanics
Zahedmanesh, Houman; Vanstreels, Kris; Gonzalez, Mario (2018)