Browsing by author "Kunnen, Eddy"
Now showing items 1-20 of 70
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15nm half-pitch patterning: EUV + SELF-aligned double patterning
Versluijs, Janko; Souriau, Laurent; Hellin, David; Orain, Isabelle; Kimura, Yoshie; Kunnen, Eddy; Dekkers, Harold; Shi, Xiaoping; Albert, Johan; Wiaux, Vincent; Xu, Kaidong (2012) -
15nm HP patterning with EUV lithography and SADP
Souriau, Laurent; Hellin, David; Kunnen, Eddy; Versluijs, Janko; Dekkers, Harold; Albert, Johan; Orain, Isabelle; Yoshie, Kimura; Xu, Kaidong; Vertommen, Johan; Wiaux, Vincent; Boullart, Werner (2012) -
2D and 3D photoresist line roughness characterization
Vaglio Pret, Alessandro; Gronheid, Roel; Kunnen, Eddy; Pargon, Erwine; Luere, Olivier; Bianchi, Davide (2012) -
2D and 3D photoresist line roughness characterization
Vaglio Pret, Alessandro; Kunnen, Eddy; Gronheid, Roel; Pargon, Erwine; Luere, Olivier; Bianchi, Davide (2013) -
A 35nm diameter vertical silicon nanowire short-gate tunnelFET
Vandooren, Anne; Rooyackers, Rita; Leonelli, Daniele; Iacopi, Francesca; De Gendt, Stefan; Verhulst, Anne; Heyns, Marc; Kunnen, Eddy; Nguyen, Duy; Demand, Marc; Ong, Patrick; Lee, Willie; Moonens, Jos; Richard, Olivier; Vandenberghe, William; Groeseneken, Guido (2009) -
A novel fully self-aligned SiGe:C HBT architecture featuring a single step epitaxial collector-base process
Donkers, Johan; Kramer, Mark; Van Huylenbroeck, Stefaan; Choi, Li Jen; Meunier-Beillard, Philippe; Boccardi, Guillaume; van Noort, W.; Hurkx, G.A.M.; Vanhoucke, Tony; Sibaja-Hernandez, Arturo; Vleugels, Frank; Winderickx, Gillis; Kunnen, Eddy; Peeters, Stefan; Baute, Debbie; De Vos, Brecht; Vandeweyer, Tom; Loo, Roger; Venegas, Rafael; Pijper, R.; Decoutere, Stefaan; Hijzen, Erwin (2007) -
A novel isolation scheme featuring cavities in the collector for a high-speed 0.13μm SiGe:C BiCMOS technology
Choi, Li Jen; Van Huylenbroeck, Stefaan; Donkers, Johan; van Noort, Wibo; Piontek, Andreas; Sibaja-Hernandez, Arturo; Meunier-Beillard, Philippe; Neuilly, Francois; Kunnen, Eddy; Leray, Philippe; Vleugels, Frank; Venegas, Rafael; Hijzen, Erwin; Decoutere, Stefaan (2007) -
A way to integrate multiple block layers for middle of line contact patterning
Kunnen, Eddy; Demuynck, Steven; Brouri, Mohand; Boemmels, Juergen; Versluijs, Janko; Ryckaert, Julien (2015) -
Active species in porous media: random walk and capture in traps
Arkhincheev, V.E.; Kunnen, Eddy; Baklanov, Mikhaïl (2011) -
Active species in porous media: random walk and capture in traps
Arkhincheev, Valeriy; Kunnen, Eddy; Baklanov, Mikhaïl (2010) -
BEOL compatible WS2 transistors fully fabricated in a 300 mm pilot line
Schram, Tom; Smets, Quentin; Heyne, Markus; Groven, Benjamin; Kunnen, Eddy; Thiam, Arame; Devriendt, Katia; Delabie, Annelies; Lin, Dennis; Chiappe, Daniele; Asselberghs, Inge; Lux, Marcel; Brus, Stephan; Huyghebaert, Cedric; Sayan, Safak; Juncker, Aurélie; Caymax, Matty; Radu, Iuliana (2017) -
CMOS patterning over high aspect ratio topographies for N10/N7 using spin-on carbon hardmasks
Hopf, Toby; Ercken, Monique; Mannaert, Geert; Kunnen, Eddy; Tao, Zheng; Vandenbroeck, Nadia; Sebaai, Farid; Kikuchi, Yoshiaki; Mertens, Hans; Kubicek, Stefan; Demuynck, Steven; Horiguchi, Naoto (2017) -
CMOS patterning over high-aspect ratio topographies for N10/N7 using spin-on carbon hardmasks
Hopf, Toby; Ercken, Monique; Mannaert, Geert; Kunnen, Eddy; Tao, Zheng; Vandenbroeck, Nadia; Sebaai, Farid; Kikuchi, Yoshiaki; Mertens, Hans; Kubicek, Stefan; Demuynck, Steven; Horiguchi, Naoto (2017) -
Contact module at dense gate pitch technology challenges
Demuynck, Steven; Mao, Ming; Kunnen, Eddy; Versluijs, Janko; Croes, Kristof; Wu, Chen; Schaekers, Marc; Peter, Antony; Kauerauf, Thomas; Teugels, Lieve; Boemmels, Juergen (2014) -
Cu resistivity scaling limits for 20 nm copper damascene lines
Van Olmen, Jan; List, Scott; Tokei, Zsolt; Carbonell, Laure; Brongersma, Sywert; Volders, Henny; Kunnen, Eddy; Heylen, Nancy; Ciofi, Ivan; Khandelwal, A.; Gelatos, J.; Mandrekar, T.; Boelen, Pieter (2007) -
Demonstration of asymmetric gate-oxide thickness four-terminal FinFETs having flexible threshold voltage and good subthreshold slope
Masahara, Meishoku; Surdeanu, Radu; Witters, Liesbeth; Doornbos, Gerben; Nguyen Hoang, Viet; Van den Bosch, Geert; Vrancken, Christa; Devriendt, Katia; Neuilly, Francois; Kunnen, Eddy; Jurczak, Gosia; Biesemans, Serge (2007-03) -
Development of 2-step plasma texturing process for crystalline silicon solar cells with Linear Microwave Plasma Sources (LPS)
Chan, BT; Kunnen, Eddy; Shamiryan, Denis; Xu, Kaidong; Boullart, Werner (2011) -
Development, optimization and evaluation of a CF4 pre-treatment process to remove unwanted interfacial layers in stacks of CVD and PECVD polycrystalline silicon-germanium for MEMS applications
Bryce, George; Severi, Simone; Van Hoof, Rita; Guo, Bin; Kunnen, Eddy; Witvrouw, Ann; Decoutere, Stefaan (2010) -
Development, optimization and evaluation of a CF4 pretreatment process to remove unwanted interfacial layers in stacks of CVD and PECVD polycrystalline silicon-germanium for MEMS applications
Bryce, George; Severi, Simone; Van Hoof, Rita; Guo, Bin; Kunnen, Eddy; Witvrouw, Ann; Decoutere, Stefaan (2010) -
Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration
Vandooren, Anne; Witters, Liesbeth; Vecchio, Emma; Kunnen, Eddy; Hellings, Geert; Peng, Lan; Inoue, Fumihiro; Li, Waikin; Waldron, Niamh; Mocuta, Dan; Collaert, Nadine (2017)