Browsing by author "Chiarella, Thomas"

Now showing items 1-20 of 130

    • 1.5×10-9 Ω·cm² Contact Resistivity on Highly Doped Si:P Using Ge Pre-amorphization and Ti Silicidation 

      Yu, Hao; Schaekers, Marc; Rosseel, Erik; Peter, Antony; Lee, Joon-Gon; Song, Woo-Bin; Demuynck, Steven; Chiarella, Thomas; Ragnarsson, Lars-Ake; Kubicek, Stefan; Everaert, Jean-Luc; Horiguchi, Naoto; Barla, Kathy; Kim, Daeyong; Collaert, Nadine; Thean, Aaron; De Meyer, Kristin (2015)

    • 1/f noise analysis of replacement metal gate bulk p-type fin field effect transistor 

      Lee, Jae Woo; Cho, Moon Ju; Simoen, Eddy; Ritzenthaler, Romain; Togo, Mitsuhiro; Boccardi, Guillaume; Mitard, Jerome; Ragnarsson, Lars-Ake; Chiarella, Thomas; Veloso, Anabela; Horiguchi, Naoto; Thean, Aaron; Groeseneken, Guido (2013-03)

    • 3D stacked IC demonstration using a through silicon via first approach 

      Van Olmen, Jan; Mercha, Abdelkarim; Katti, Guruprasad; Huyghebaert, Cedric; Van Aelst, Joke; Seppala, Emma; Zhao, Chao; Armini, Silvia; Vaes, Jan; Cotrin Teixeira, Ricardo; Van Cauwenberghe, Marc; Verdonck, Patrick; Verhemeldonck, Koen; Jourdain, Anne; Ruythooren, Wouter; de Potter de ten Broeck, Muriel; Opdebeeck, Ann; Chiarella, Thomas; Parvais, Bertrand; Debusschere, Ingrid; Hoffmann, Thomas Y.; De Wachter, Bart; Dehaene, Wim; Stucchi, Michele; Rakowski, Michal; Soussan, Philippe; Cartuyvels, Rudi; Beyne, Eric; Biesemans, Serge; Swinnen, Bart (2008)

    • 3D-carrier profiling and parasitic resistance analysis in vertically stacked gate-all-around Si nanowire CMOS transistors 

      Eyben, Pierre; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Veloso, Anabela; Mertens, Hans; Pena, Vanessa; Santoro, Gaetano; Machillot, Jerome; Kim, Myungsun; Miyashita, Toshihiko; Yoshida, Naomi; Bender, Hugo; Richard, Olivier; Celano, Umberto; Paredis, Kristof; Wouters, Lennaert; Mitard, Jerome; Horiguchi, Naoto (2019)

    • 3D-carrier profiling in FinFETs using scanning spreading resistance microscopy 

      Mody, Jay; Zschaetzsch, Gerd; Koelling, Sebastian; De Keersgieter, An; Eneman, Geert; Kambham, Ajay Kumar; Drijbooms, Chris; Schulze, Andreas; Chiarella, Thomas; Horiguchi, Naoto; Hoffmann, Thomas; Eyben, Pierre; Vandervorst, Wilfried (2011)

    • 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS 

      Witters, Liesbeth; Takeoka, Shinji; Yamaguchi, Shinpei; Hikavyy, Andriy; Shamiryan, Denis; Cho, Moon Ju; Chiarella, Thomas; Ragnarsson, Lars-Ake; Loo, Roger; Kerner, Christoph; Crabbe, Yvo; Franco, Jacopo; Tseng, Joshua; Wang, Wei-E; Rohr, Erika; Schram, Tom; Richard, Olivier; Bender, Hugo; Biesemans, Serge; Absil, Philippe; Hoffmann, Thomas Y. (2010)

    • A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs 

      Mitard, Jerome; Witters, Liesbeth; Sasaki, Yuichiro; Arimura, Hiroaki; Schulze, Andreas; Loo, Roger; Ragnarsson, Lars-Ake; Hikavyy, Andriy; Cott, Daire; Chiarella, Thomas; Kubicek, Stefan; Mertens, Hans; Ritzenthaler, Romain; Vrancken, Christa; Favia, Paola; Bender, Hugo; Horiguchi, Naoto; Barla, Kathy; Mocuta, Dan; Mocuta, Anda; Collaert, Nadine; Thean, Aaron (2016-06)

    • A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions 

      Sasaki, Yuichiro; Ritzenthaler, Romain; De Keersgieter, An; Chiarella, Thomas; Kubicek, Stefan; Rosseel, Erik; Waite, Andrew; del Agua Borniquel, Jose Ignacio; Colombeau, Benjamin; Chew, Soon Aik; Kim, Min-Soo; Schram, Tom; Demuynck, Steven; Vandervorst, Wilfried; Horiguchi, Naoto; Mocuta, Dan; Mocuta, Anda; Thean, Aaron (2015-06)

    • A low cost 90nm RF-CMOS platform for record RF circuit performance 

      Jeamsaksiri, Wutthinan; Linten, Dimitri; Thijs, Steven; Carchon, Geert; Ramos, Javier; Mercha, Abdelkarim; Sun, Xiao; Soussan, Philippe; Dehan, Morin; Chiarella, Thomas; Venegas, Rafael; Subramanian, Vaidy; Scholten, A.; Wambacq, Piet; Velghe, Rudolf; Mannaert, Geert; Heylen, Nancy; Verbeeck, Rita; Boullart, Werner; Heyvaert, Ilse; Mahadeva Iyer, Natarajan; Groeseneken, Guido; Debusschere, Ingrid; Biesemans, Serge; Decoutere, Stefaan (2005-06)

    • A Pragmatic Model to Predict Future Device Aging 

      Brown, James; Tok, Kean Hong; Gao, Rui; Ji, Zhigang; Zhang, Weidong; Marsland, John S.; Chiarella, Thomas; Franco, Jacopo; Kaczer, Ben; Linten, Dimitri; Zhang, Jian Fu (2023)

    • Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations 

      Eyben, Pierre; Matagne, Philippe; Chiarella, Thomas; De Keersgieter, An; Kubicek, Stefan; Mitard, Jerome; Mocuta, Anda; Horiguchi, Naoto; Thean, Aaron; Mocuta, Dan (2016)

    • Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT 

      Rothschild, Aude; Shi, Xiaoping; Everaert, Jean-Luc; Kerner, Christoph; Chiarella, Thomas; Hoffmann, Thomas; Vrancken, Christa; Shickova, Adelina; Yoshinao, H.; Mitsuhashi, Riichirou; Niwa, Masaaki; Lauwers, Anne; Veloso, Anabela; Kittl, Jorge; Absil, Philippe; Biesemans, Serge (2007)

    • Addressing key concerns for implementation of Ni FUSI into manufacturing for 45/32 nm CMOS 

      Shickova, Adelina; Kauerauf, Thomas; Rothschild, Aude; Aoulaiche, Marc; Sahhaf, Sahar; Kaczer, Ben; Veloso, Anabela; Torregiani, Cristina; Pantisano, Luigi; Lauwers, Anne; Zahid, Mohammed; Rost, Tim; Tigelaar, H.; Pas, M.; Fretwell, J.; McCormack, J.; Hoffmann, Thomas; Kerner, Christoph; Chiarella, Thomas; Brus, Stephan; Harada, Yoshinao; Niwa, Masaaki; Kaushik, Vidya; Maes, Herman; Absil, Philippe; Groeseneken, Guido; Biesemans, Serge; Kittl, Jorge (2007)

    • ALD High-k growth on Ge substrates 

      Delabie, Annelies; Brijs, Bert; Caymax, Matty; Chiarella, Thomas; Conard, Thierry; Puurunen, Riikka; Richard, Olivier; Van Steenbergen, Jan; Teerlinck, Ivo; Zhao, Chao; Heyns, Marc; Meuris, Marc (2003)

    • Analog performance and its variability in sub-10 nm fin-width FinFETs: a detailed analysis 

      Bhoir, Mandar S.; Chiarella, Thomas; Ragnarsson, Lars-Ake; Mitard, Jerome; Terzieva, Valentina; Horiguchi, Naoto; Mohapatra, Nihar R. (2019)

    • Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession 

      Chiarella, Thomas; Witters, Liesbeth; Mercha, Abdelkarim; Kerner, Christoph; Rakowski, Michal; Ortolland, Claude; Ragnarsson, Lars-Ake; Parvais, Bertrand; De Keersgieter, An; Kubicek, Stefan; Redolfi, Augusto; Vrancken, Christa; Brus, Stephan; Lauwers, Anne; Absil, Philippe; Biesemans, Serge; Hoffmann, Thomas Y. (2010)

    • Buried power rail integration with FinFETs for ultimate CMOS scaling 

      Gupta, Anshul; Varela Pedreira, Olalla; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, Katia; Hanssen, Frederik; Tao, Zheng; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, Noemie; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min-Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Cousserier, Joris; Yakimets, Dmitry; Lazzarino, Frederic; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Jaysankar, Manoj; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Boemmels, Juergen; Demuynck, Steven; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node 

      Gupta, Anshul; Mertens, Hans; Tao, Zheng; Demuynck, Steven; Boemmels, Juergen; Arutchelvan, Goutham; Devriendt, Katia; Varela Pedreira, Olalla; Ritzenthaler, Romain; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebaai, Farid; Lorant, Christophe; Jourdan, Nicolas; Chan, BT; Zahedmanesh, Houman; Subramanian, Sujith; Schleicher, Filip; Hopf, Toby; Peter, Antony; Rassoul, Nouredine; Debruyn, Haroen; Demonie, Ingrid; Siew, Yong Kong; Chiarella, Thomas; Briggs, Basoene; Zhou, Daisy; Rosseel, Erik; De Keersgieter, An; Capogreco, Elena; Dentoni Litta, Eugenio; Boccardi, Guillaume; Baudot, Sylvain; Mannaert, Geert; Bontemps, N.; Sepulveda Marquez, Alfonso; Mertens, Sofie; Kim, Min Soo; Dupuy, Emmanuel; Vandersmissen, Kevin; Paolillo, Sara; Yakimets, Dmitry; Chehab, Bilal; Favia, Paola; Drijbooms, Chris; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frederic; Morin, Pierre; Altamirano Sanchez, Efrain; Mitard, Jerome; Wilson, Chris; Holsteyns, Frank; Tokei, Zsolt; Horiguchi, Naoto (2020)

    • Carbon-based thermal stabilization techniques for junction and silicide engineering for high performance CMOS periphery in memory applications 

      Ortolland, Claude; Mathew, Suraj; Duffy, Ray; Saino, Kanta; Kim, Chul Sung; Mertens, Sofie; Horiguchi, Naoto; Vrancken, Christa; Chiarella, Thomas; Kerner, Christoph; Absil, Philippe; Lauwers, Anne; Biesemans, Serge; Hoffmann, Thomas Y. (2009)

    • CDM-time domain turn-on transient of ESD diodes in bulk FinFET and GAA NW technologies 

      Chen, Shih-Hung; Linten, Dimitri; Hellings, Geert; Simicic, Marko; Kaczer, Ben; Chiarella, Thomas; Mertens, Hans; Mitard, Jerome; Mocuta, Anda; Horiguchi, Naoto (2019)