Browsing by author "De Vos, Joeri"
Now showing items 1-20 of 106
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3D stacking induced mechanical stress effects
Cherman, Vladimir; Van der Plas, Geert; De Vos, Joeri; Ivankovic, Andrej; Lofrano, Melina; Simons, Veerle; Gonzalez, Mario; Vanstreels, Kris; Wang, Teng; Daily, Robert; Guo, Wei; Beyer, Gerald; La Manna, Antonio; De Wolf, Ingrid; Beyne, Eric (2014) -
3D Wafer-to-Wafer Bonding Thermal Resistance Comparison: Hybrid Cu/dielectric Bonding versus Dielectric via-last Bonding
Oprins, Herman; Cherman, Vladimir; Webers, Tomas; Kim, Soon-Wook; de Vos, Joeri; Van der Plas, Geert; Beyne, Eric (2020) -
A complementary high-voltage technology based on n-type CdSe:In and p-type Ge:Cu thin film transistors
De Cubber, A. M.; De Smet, Herbert; De Vos, Joeri; Carchon, Nadine; Van Calster, Andre (1996) -
A fully planar stacked gate flash technology with T-shaped floating gate for increased cell coupling ratio
De Vos, Joeri; Haspeslagh, Luc; Blomme, Pieter; Demand, Marc; Devriendt, Katia; Vleugels, Frank; Wellekens, Dirk; Van Houdt, Jan (2007) -
A highly reliable 1.4μm pitch via-last TSV module for wafer-to-wafer hybrid bonded 3D-SOC systems
Van Huylenbroeck, Stefaan; De Vos, Joeri; El-Mekki, Zaid; Jamieson, Geraldine; Tutunjyan, Nina; Muga, Karthik; Stucchi, Michele; Miller, Andy; Beyer, Gerald; Beyne, Eric (2019) -
A highly reliable 1×5μm via-last TSV module
Van Huylenbroeck, Stefaan; Li, Yunlong; De Vos, Joeri; Jamieson, Geraldine; Tutunjyan, Nina; Miller, Andy; Beyer, Gerald; Beyne, Eric (2018) -
A low-cost poly-sidewall erase HIMOSTM technology for 130-90nm embedded flash memories
Van Houdt, Jan; Haspeslagh, Luc; Wellekens, Dirk; De Vos, Joeri; Hendrickx, Paul; Tsouhlarakis, Jorgo (2004) -
A new 2 isolated-bits/cell Flash memory device with self aligned split gate structure using ONO stacks for charge storage
Breuil, Laurent; Schuler, Franz; Haspeslagh, Luc; Wellekens, Dirk; De Vos, Joeri; Lorenzini, Martino; Van Houdt, Jan (2003) -
A new scalable self-aligned dual-bit split-gate charge trapping memory device
Breuil, Laurent; Haspeslagh, Luc; Blomme, Pieter; Wellekens, Dirk; De Vos, Joeri; Lorenzini, Martino; Van Houdt, Jan (2005) -
A Study of SiCN Wafer-to-Wafer Bonding and Impact of Wafer Warpage
Iacovo, Serena; D'have, Koen; Okudur, Oguzhan Orkut; De Vos, Joeri; Uhrmann, Thomas; Plach, Thomas; Conard, Thierry; Meersschaut, Johan; Bex, Pieter; Brems, Steven; Phommahaxay, Alain; Gonzalez, Mario; Witters, Liesbeth; Beyer, Gerald; Beyne, Eric (2023) -
A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring
Araga, Yuuki; Miura, Ranto; Nagata, Makoto; Roda Neve, Cesar; De Vos, Joeri; Van der Plas, Geert; Beyne, Eric (2014) -
A study on substrate noise coupling among TSVs in 3D chip stack
Araga, Yuuki; Nagata, Makoto; De Vos, Joeri; Van der Plas, Geert; Beyne, Eric (2018) -
Advanced experimental Back-End-Of-Line (BEOL) stability test: measurements and simulations
Vanstreels, Kris; Cherman, Vladimir; Gonzalez, Mario; De Wolf, Ingrid; Van der Plas, Geert; De Vos, Joeri; Boemmels, Juergen; Tokei, Zsolt (2015) -
Advanced experimental BEOL stability test: measurements and simulations
Vanstreels, Kris; Cherman, Vladimir; Gonzalez, Mario; De Wolf, Ingrid; Van der Plas, Geert; De Vos, Joeri; Boemmels, Juergen; Tokei, Zsolt (2014) -
Advances in SiCN-SiCN bonding with high accuracy wafer-to-wafer (W2W) stacking technology
Peng, Lan; Kim, Soon-Wook; Iacovo, Serena; Inoue, Fumihiro; Phommahaxay, Alain; Sleeckx, Erik; De Vos, Joeri; Zinner, Dominik; Thomas, Wagenleitner; Thomas, Uhrmann; Markus, Wimplinger; Ben, Schoenaers; Andre, Stesmans; Afanasiev, Valeri; Miller, Andy; Beyer, Gerald; Beyne, Eric (2018) -
An efficient bump pad design to mitigate the flip chip package induced stress
Gonzalez, Mario; De Vos, Joeri; Van der Plas, Geert; Beyne, Eric (2015) -
Anomalous C-V inversion in TSV's: The problem and its cure
Stucchi, Michele; De Vos, Joeri; Jourdain, Anne; Li, Yunlong; Van der Plas, Geert; Croes, Kristof; Beyne, Eric (2018) -
Backside illuminated hybrid FPA achieving low cross-talk combined with high QE
De Munck, Koen; Ramachandra Rao, Padmakumar; Minoglou, Kiki; De Vos, Joeri; Sabuncuoglu Tezcan, Deniz; De Moor, Piet (2011) -
Characterization of bonding activation sequences to enable ultra-low Cu/SiCN wafer level hybrid bonding
Iacovo, Serena; Peng, Lan; Nagano, Fuya; Uhrmann, Thomas; Burggraf, Jurgen; Fehkuhrer, Andreas; Conard, Thierry; Inoue, Fumihiro; Kim, Soon-Wook; De Vos, Joeri; Phommahaxay, Alain; Beyne, Eric (2021) -
Characterization of extreme Si thinning proces for wafer-to-wafer stacking
Inoue, Fumihiro; Jourdain, Anne; De Vos, Joeri; Peng, Lan; Liebens, Maarten; Armini, Silvia; Uedono, Akira; Rebibis, Kenneth June; Miller, Andy; Beyne, Eric; Sleeckx, Erik (2016)