Browsing by author "Swinnen, Bart"

3-D technology assessment: path-finding the technology/design sweet-spot

Marchal, Pol; Bougard, Bruno; Katti, Guruprasad; Stucchi, Michele; Dehaene, Wim; Papanikolaou, Antonis; Verkest, Diederik; Swinnen, Bart; Beyne, Eric (2009)

300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications

Jourdain, Anne; Buisson, Thibault; Phommahaxay, Alain; Privett, Marc; Wallace, Daniel; Sood, Sumant; Bisson, Peter; Beyne, Eric; Travaly, Youssef; Swinnen, Bart (2010-11)

3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps

Guo, Wei; Van der Plas, Geert; Ivankovic, Andrej; Eneman, Geert; Cherman, Vladimir; De Wachter, Bart; Mercha, Abdelkarim; Gonzalez, Mario; Civale, Yann; Redolfi, Augusto; Buisson, Thibault; Jourdain, Anne; Vandevelde, Bart; Rebibis, Kenneth June; De Wolf, Ingrid; La Manna, Antonio; Beyer, Gerald; Beyne, Eric; Swinnen, Bart (2012)

3D integration technology developments at IMEC

De Moor, Piet; Ruythooren, Wouter; Soussan, Philippe; Baert, Kris; Van Hoof, Chris; Swinnen, Bart; Beyne, Eric (2007-11)

3D Integration: IMEC's collaborative research program model

Swinnen, Bart (2009)

3D stacked IC demonstration using a through silicon via first approach

Van Olmen, Jan; Mercha, Abdelkarim; Katti, Guruprasad; Huyghebaert, Cedric; Van Aelst, Joke; Seppala, Emma; Zhao, Chao; Armini, Silvia; Vaes, Jan; Cotrin Teixeira, Ricardo; Van Cauwenberghe, Marc; Verdonck, Patrick; Verhemeldonck, Koen; Jourdain, Anne; Ruythooren, Wouter; de Potter de ten Broeck, Muriel; Opdebeeck, Ann; Chiarella, Thomas; Parvais, Bertrand; Debusschere, Ingrid; Hoffmann, Thomas Y.; De Wachter, Bart; Dehaene, Wim; Stucchi, Michele; Rakowski, Michal; Soussan, Philippe; Cartuyvels, Rudi; Beyne, Eric; Biesemans, Serge; Swinnen, Bart (2008)

3D stacked IC demonstrator using hybrid collective die-to-wafer bonding with copper through silicon vias (TSV)

Van Olmen, Jan; Coenen, Jens; Dehaene, Wim; De Meyer, Kristin; Huyghebaert, Cedric; Jourdain, Anne; Katti, Guruprasad; Mercha, Abdelkarim; Rakowski, Michal; Stucchi, Michele; Travaly, Youssef; Beyne, Eric; Swinnen, Bart (2009)

3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding

Katti, Guruprasad; Mercha, Abdelkarim; Van Olmen, Jan; Huyghebaert, Cedric; Jourdain, Anne; Stucchi, Michele; Rakowski, Michal; Debusschere, Ingrid; Soussan, Philippe; Dehaene, Wim; De Meyer, Kristin; Travaly, Youssef; Beyne, Eric; Biesemans, Serge; Swinnen, Bart (2009)

3D system integration technologies

Beyne, Eric; Swinnen, Bart (2007)

3D Technologies: requiring more than 3 dimensions from concept to product

Swinnen, Bart (2009)

3D Wafer level packaging: processes and materials for through silicon-vias and thin die embedding

Soussan, Philippe; Sabuncuoglu Tezcan, Deniz; Iker, Francois; Ruythooren, Wouter; Swinnen, Bart; Majeed, Bivragh; Beyne, Eric (2009)

3D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias

Civale, Yann; Sabuncuoglu Tezcan, Deniz; Philipsen, Harold; Duval, Fabrice; Jaenen, Patrick; Travaly, Youssef; Soussan, Philippe; Swinnen, Bart; Beyne, Eric (2011)

A new scaled through Si via with polymer fill for 3D wafer level packaging

Sabuncuoglu Tezcan, Deniz; Duval, Fabrice; Luhn, Ole; Soussan, Philippe; Swinnen, Bart (2008)

Advanced technologies for in-line and post-processed TSV integration

Beyne, Eric; Swinnen, Bart; Van Olmen, Jan; Sabuncuoglu Tezcan, Deniz (2009)

Analysis of the induced stresses in silicon during thermocompression Cu-Cu bonding of Cu-through-vias in 3D-SIC architecture

Okoro, Chukwudi; Eneman, Geert; Gonzalez, Mario; Vandevelde, Bart; Swinnen, Bart; Stoukatch, Serguei; Beyne, Eric; Vandepitte, Dirk (2007-05)