Sub-20nm gate length p-FinFETs device performance improvement using TEM/EDX and NBD based TCAD calibrations.

Abstract

In this paper we analyze how an improved SiGe p-epi source/drain engineering can enhance the performance of sub-20nm gate length p-FinFETs. In the proposed ap-proach, Drift-Diffusion TCAD simulations are calibrated based on advanced metrology and on Monte-Carlo simu-lations such that the resulting simulated ID-VG matches the one measured on device. Calibrated TCAD simulator is then used to understand the limited performances of the device and to propose new source/drain epi architectures with graded and increased Ge content. A new p-FinFET design is fabricated and tested, confirming a boost in ON-current and a reduction of the access resistance. Pro-spective TCAD work is also performed to suggest possible future improvements.