Browsing by Author "Aoulaiche, Marc"

2D and 3D Fully-depleted extension-less devices for advanced logic and memory applications

A Low frequency noise characterization in n-channel UTBOX devices with 6 nm Si film

A low-power HKMG CMOS platform compatible with DRAM node 2x and beyond

A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C

A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies

A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 10^16 endurance at 85°C

Addressing key concerns for implementation of Ni FUSI into manufacturing for 45/32 nm CMOS

Advanced dielectrics targeting 2X DRAM MIM capacitors

Advanced doping techniques for DRAM peripheral MOSFETs

Advanced electrical characterization toward (sub) 1nm EOT HfSiON – hole trapping in PFET and L-dependent effects

Advanced PBTI reliability with 0.69nm EOT GdHfO gate dielectric

Advanced USJ for high-k / metal gate CMOS devices

Advantages of different source/drain engineering on scaled UTBOX FD SOI nMOSFETs at high temperature operation

Analog parameters of MuGFET devices with different source/drain engineering

Analysis of sense margin and reliability of 1T-DRAM fabricated on thin-film UTBOX substrates

Analysis of UTBOX-1T DRAM memory cell at high temperatures

Analytical model for anomalous positive bias temperature instability in La-based HfO2 nFETs based on independent characterization of charging components

Analytical model for anomalous positive bias temperature instability in La-based HfO2 nFETs based on independent characterization of charging components

Anomalous positive-bias temperature instability of high-k/metal gate devices with Dy2O3 capping

Anomalous positive-bias temperature instability of high-k/metal gate nMOSFET devices with Dy2O3 capping