Browsing by Author "Augendre, Emmanuel"
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Publication 60 MeV proton irradiation effects on NO-annealed and standard-oxide deep submicron MOSFETs
Oral presentation2001, RADECS; 10-14 September 2001; Grenoble, France.Publication A high performance 0.18µm elevated source/drain technology with improved manufacturability
Proceedings paper1999, ESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference, 13/09/1999, p.636-639Publication A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM
;von Arnim, Klaus ;Augendre, Emmanuel ;Pacha, C. ;Schulz, Thomas ;San, Kemal TamerBauer, F.Proceedings paper2007, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2007, p.106-107Publication A new dummy-free shallow trench isolation concept for mixed-signal applications
;Badenes, Gonçal ;Rooyackers, Rita ;Augendre, Emmanuel ;Vandamme, EwoutPerello, CarlesProceedings paper1999, ULSI Process Integration. Proceedings of the First International Symposium, 17/10/1999, p.231-241Publication A new dummy-free shallow trench isolation concept for mixed-signal applications
;Badenes, Gonçal ;Rooyackers, Rita ;Augendre, Emmanuel ;Vandamme, EwoutPerello, CarlesJournal article2000, Journal of the Electrochemical Society, (147) 10, p.3287-3282Publication A reliable metric for mobility extraction of short channel MOSFETs
Journal article2007, IEEE Transaction Electron Devices, (54) 10, p.2690-2698Publication A simulation evaluation of 100 nm CMOS device performance
;Jones, S. K. ;Bazley, D. J. ;Augendre, Emmanuel ;Badenes, Gonçal; Skotnicki, T.Proceedings paper2001, Proceedings of the International Conference on Simulation of Semiconductor Physics and Processes - SISPAD, 5/09/2001, p.288-291Publication Advanced CMOS device technologies for 45nm node and below
Journal article2007, Science and Technology of Advanced Materials, (8) 3, p.214-218Publication Analysis and optimisation of the 2D-dopant profile in a 90 nm CMOS technology using scanning spreading resistance microscopy
Meeting abstract2003, Ultra Shallow Junctions. 7th Int. Worksh. Fabrication, Characterization and Modeling of Ultra Shallow Doping Profiles in Semic., 27/04/2003, p.183Publication Analysis of the two-dimensional-dopant profile in a 90 nm complementary metal-oxide-semiconductor technology using scanning spreading resistance microscopy
Journal article2004-01, Journal of Vacuum Science & Technology B, (22) 1, p.364-368Publication Arsenic and phosphorus co-implantation for deep-submicron CMOS gate and source/drain engineering
Proceedings paper2001, Proceedings of the 31st European Solid-State Device Research Conference, 11/09/2001, p.115-118Publication Arsenic junction thermal stability and high-dose boron-pocket activation during SPER in nMOS transistors
Journal article2007, IEEE Electron Device Letters, (28) 3, p.198-200Publication Challenges in scaling of CMOS devices towards 65nm node
Proceedings paper2003-06, Diagnostic and Yield, 23/06/2003Publication CMOS device optimisation for mixed-signal technologies
;Stolk, Peter ;Tuinhout, Hans ;Duffy, Ray ;Augendre, Emmanuel ;Bellefroid, L. P.Bolt, M. J. B.Proceedings paper2001, IEDM Technical Digest, 2/12/2001, p.215-218Publication CMOS integration results for the 90nm technology node
Journal article2003, Semiconductor Fabtech, 18, p.129-132Publication Controlling STI-related parasitic conduction in 90nm CMOS and below
Proceedings paper2002, ESSDERC - 32nd European Solid-State Device Research Conference, 24/09/2002, p.507-510Publication Demonstration of fully Ni-silicided metal gates on HfO2 based high-k gate dielectrics as a candidate for low power applications
Proceedings paper2004-06, Technical Digest VLSI Technology Symposium, 15/06/2004, p.190-191Publication Demonstration of Ni fully GermanoSilicide as a pFET gate electrode candidate on HfSiON
Proceedings paper2005, Technical Digest International Electron Devices Meeting (IEDM), 5/12/2005, p.27/05/2001-27/05/2004Publication Direct measurement of MOSFET channel strain by means of backside etching and Raman spectroscopy on long-channel devices
Journal article2010, IEEE Electron Device Letters, (31) 5, p.419-421Publication Doubling or quadrupling MuGFET Fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency
Oral presentation2007, IEEE International Solid-State Circuits Conference - ISSCC
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