Browsing by Author "Jourdan, Nicolas"

12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices

21 nm Pitch dual-damascene BEOL process integration with full barrierless Ru metallization

300mm wafer level CVD-Mn/iodine-CVD-Cu-based metallization study for advanced copper interconnections

Alternative metal recess for fully-self-aligned-vias

Automated voids detection for metal filled trenches with bottom CD of 10nm

Backside Power Delivery With Relaxed Overlay for Backside Patterning Using Extreme Wafer Thinning and Molybdenum-Filled Slit Nano Through Silicon Vias

Barrier/liner stacks for scaling the Cu interconnect metallization

Buried Power Rail Integration for CMOS Scaling beyond the 3 nm Node

Buried power rail integration with FinFETs for ultimate CMOS scaling

Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node

Buried Power Rail Metal exploration towards the 1 nm Node

Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond

Co and Ru dual damascene compatible metallization studies

Cobalt and Ruthenium drift in ultra-thin oxides

Copper-ruthenium system study for advanced hybrid BEOL -interconnects applications

Cu resistivity and intrinsic EM-reliability study in Ta/Cu, Co/Cu and Ru/Cu systems for advanced BEOL Cu interconnections

Cu wire resistance improvement using Mn-based self-formed barriers

CVD Mn-based barrier for advanced copper interconnect technology: integration study

CVD Mn-based self-formed barrier for advanced interconnect technology

CVD-Mn(Nx) as copper diffusion barrier for advanced interconnect technologies