Browsing by Author "Mocuta, Dan"
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Publication 12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices
; ;Harada, N.; ; ; Huynh Bao, TrongProceedings paper2019, 2019 Symposium on VLSI Technology, 9/06/2019, p.T15-1Publication 3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
; ; ; ; ; Journal article2018-11, IEEE Transactions on Electron Devices, (65) 11, p.5165-5171Publication 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
; ; ; ; ; Proceedings paper2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.69-70Publication 3D technologies for analog/RF applications
Proceedings paper2017, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - IEEE S3S, 16/10/2017, p.13.1Publication A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs
Proceedings paper2016-06, IEEE Symposium on VLSI Technology, 13/06/2016, p.34-35Publication A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions
Proceedings paper2015-06, IEEE Symposium on VLSI Technology, 15/06/2015, p.30-31Publication A million wafer, virtual fabrication approach to determine process capability requirements for an industry-standard 5nm BEOL two-level metal flow
Proceedings paper2016, International Conference on Simulation of Semiconductor Processes and Devices - SISPAD, 6/09/2016, p.43-46Publication A near- & short-wave IR tunable InGaAs nanomembrane photoFET on flexible substrate for lightweight and wide-angle imaging applications
Proceedings paper2018, VLSI Technology Symposium, 18/06/2018, p.159-160Publication A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation
Proceedings paper2019-06, 2019 Symposia on VLSI Technology and Circuits, 9/06/2019, p.T92-T93Publication Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations
Proceedings paper2016, International Conference on Simulation of Semiconductor Processes and Devices - SISPAD, 6/09/2016, p.287-290Publication Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET
Proceedings paper2018, IEEE International Electron Devices Meeting - IEDM, 1/12/2018, p.496-499Publication Analysis of diffusion mechanisms for SSD in confined volumes : An alternative solution for extension formation in N7 and N5 technologies
Meeting abstract2018, E-MRS Spring Symposium I: Materials Research for Group IV Semiconductors: Growth, Characterization and Technological Development, 18/06/2018, p.I.15.5Publication Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
Proceedings paper2019, 2019 Symposia on VLSI Technology and Circuits, 9/06/2019, p.T56-T57Publication Challenges and opportunities for vertical nanowire FETs: device design and fabrication
Proceedings paper2018, 50th International Conference on Solid State Devices and Materials - SSDM, 9/09/2018, p.159-160Publication Challenges and opportunities of vertical FET devices using 3D circuit design layouts
Proceedings paper2016, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - S3S, 10/10/2016, p.1-3Publication Challenges and progresses in high-k metal gate for Silicon-based advanced CMOS transistor architecture
Proceedings paper2017, International Workshop on Dielectric Thin Films, 20/11/2017, p.102-103Publication Challenges on surface conditioning in 3D device architectures: triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs
Proceedings paper2017, 232nd ECS Fall Meeting - 15th International Symposium on Semiconductor Cleaning Science and Technology - SCST15, 1/10/2017, p.3-20Publication Challenges on surface conditioning in 3D device architectures: triple-gate finFETs, gate-all-around lateral and vertical nanowireFETs
Meeting abstract2017, 15th International Symposium on Semiconductor Cleaning Science and Technology at the 232nd ECS Fall Meeting, 1/10/2017, p.1055Publication Comprehensive study of Ga Activation in Si, SiGe and Ge and 5 x 10-10 $Xcm2 contact resistivity achieved on Ga doped Ge using nanosecond laser activation
Proceedings paper2017, IEEE International Electron Devices Meeting - IEDM, 2/12/2017, p.550-552Publication Cost effective FinFET platform for stand alone DRAM 1Y and beyond memory periphery
Proceedings paper2018-01, 2018 IEEE International Memory Workshop (IMW), 13/05/2018, p.1-4