Repository logo Institutional repository
  • Communities & Collections
  • Browse
  • Site
Search repository
High contrast
  1. Home
  2. Browse by Author

Browsing by Author "Mocuta, Dan"

Filter results by typing the first few letters
Now showing 1 - 20 of 112
  • Results Per Page
  • Sort Options
  • Loading...
    Thumbnail Image
    Publication

    12-EUV layer Surrounding Gate Transistor (SGT) for vertical 6-T SRAM: 5-nm-class technology for ultra-density logic devices

    Kim, Min-Soo  
    ;
    Harada, N.
    ;
    Kikuchi, Yoshiaki  
    ;
    Boemmels, Juergen  
    ;
    Mitard, Jerome  
    ;
    Huynh Bao, Trong
    Proceedings paper
    2019, 2019 Symposium on VLSI Technology, 9/06/2019, p.T15-1
  • Loading...
    Thumbnail Image
    Publication

    3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability

    Vandooren, Anne  
    ;
    Franco, Jacopo  
    ;
    Parvais, Bertrand  
    ;
    Wu, Zhicheng  
    ;
    Witters, Liesbeth  
    ;
    Walke, Amey  
    Journal article
    2018-11, IEEE Transactions on Electron Devices, (65) 11, p.5165-5171
  • Loading...
    Thumbnail Image
    Publication

    3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

    Vandooren, Anne  
    ;
    Franco, Jacopo  
    ;
    Parvais, Bertrand  
    ;
    Wu, Zhicheng  
    ;
    Witters, Liesbeth  
    ;
    Walke, Amey  
    Proceedings paper
    2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.69-70
  • Loading...
    Thumbnail Image
    Publication

    3D technologies for analog/RF applications

    Vandooren, Anne  
    ;
    Parvais, Bertrand  
    ;
    Witters, Liesbeth  
    ;
    Walke, Amey  
    ;
    Vais, Abhitosh  
    Proceedings paper
    2017, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - IEEE S3S, 16/10/2017, p.13.1
  • Loading...
    Thumbnail Image
    Publication

    A 2nd generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs

    Mitard, Jerome  
    ;
    Witters, Liesbeth  
    ;
    Sasaki, Yuichiro
    ;
    Arimura, Hiroaki  
    ;
    Schulze, Andreas
    Proceedings paper
    2016-06, IEEE Symposium on VLSI Technology, 13/06/2016, p.34-35
  • Loading...
    Thumbnail Image
    Publication

    A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions

    Sasaki, Yuichiro
    ;
    Ritzenthaler, Romain  
    ;
    De Keersgieter, An  
    ;
    Chiarella, Thomas  
    ;
    Kubicek, Stefan  
    Proceedings paper
    2015-06, IEEE Symposium on VLSI Technology, 15/06/2015, p.30-31
  • Loading...
    Thumbnail Image
    Publication

    A million wafer, virtual fabrication approach to determine process capability requirements for an industry-standard 5nm BEOL two-level metal flow

    Clark, William
    ;
    Juncker, Aurelie
    ;
    Paladugu, E.
    ;
    Fried, David
    ;
    Wilson, Chris  
    ;
    Pourtois, Geoffrey  
    Proceedings paper
    2016, International Conference on Simulation of Semiconductor Processes and Devices - SISPAD, 6/09/2016, p.43-46
  • Loading...
    Thumbnail Image
    Publication

    A near- & short-wave IR tunable InGaAs nanomembrane photoFET on flexible substrate for lightweight and wide-angle imaging applications

    Li, Yida
    ;
    Alian, AliReza  
    ;
    Huang, Li  
    ;
    Ang, Kah Wee
    ;
    Lin, Dennis  
    ;
    Mocuta, Dan
    ;
    Collaert, Nadine  
    Proceedings paper
    2018, VLSI Technology Symposium, 18/06/2018, p.159-160
  • Loading...
    Thumbnail Image
    Publication

    A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation

    Arimura, Hiroaki  
    ;
    Cott, Daire  
    ;
    Boccardi, Guillaume  
    ;
    Loo, Roger  
    ;
    Wostyn, Kurt  
    ;
    Brus, Stephan  
    Proceedings paper
    2019-06, 2019 Symposia on VLSI Technology and Circuits, 9/06/2019, p.T92-T93
  • Loading...
    Thumbnail Image
    Publication

    Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations

    Eyben, Pierre  
    ;
    Matagne, Philippe  
    ;
    Chiarella, Thomas  
    ;
    De Keersgieter, An  
    ;
    Kubicek, Stefan  
    Proceedings paper
    2016, International Conference on Simulation of Semiconductor Processes and Devices - SISPAD, 6/09/2016, p.287-290
  • Loading...
    Thumbnail Image
    Publication

    Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET

    Arimura, Hiroaki  
    ;
    Eneman, Geert  
    ;
    Capogreco, Elena  
    ;
    Witters, Liesbeth  
    ;
    De Keersgieter, An  
    Proceedings paper
    2018, IEEE International Electron Devices Meeting - IEDM, 1/12/2018, p.496-499
  • Loading...
    Thumbnail Image
    Publication

    Analysis of diffusion mechanisms for SSD in confined volumes : An alternative solution for extension formation in N7 and N5 technologies

    Eyben, Pierre  
    ;
    Pawlak, Bartek  
    ;
    De Keersgieter, An  
    ;
    Kikuchi, Yoshiaki  
    ;
    Mitard, Jerome  
    Meeting abstract
    2018, E-MRS Spring Symposium I: Materials Research for Group IV Semiconductors: Growth, Characterization and Technological Development, 18/06/2018, p.I.15.5
  • Loading...
    Thumbnail Image
    Publication

    Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications

    Vandooren, Anne  
    ;
    Wu, Zhicheng  
    ;
    Khaled, Ahmad  
    ;
    Franco, Jacopo  
    ;
    Parvais, Bertrand  
    ;
    Li, W.
    Proceedings paper
    2019, 2019 Symposia on VLSI Technology and Circuits, 9/06/2019, p.T56-T57
  • Loading...
    Thumbnail Image
    Publication

    Challenges and opportunities for vertical nanowire FETs: device design and fabrication

    Veloso, Anabela  
    ;
    Matagne, Philippe  
    ;
    Huynh Bao, Trong
    ;
    Eneman, Geert  
    ;
    Loo, Roger  
    ;
    Wostyn, Kurt  
    Proceedings paper
    2018, 50th International Conference on Solid State Devices and Materials - SSDM, 9/09/2018, p.159-160
  • Loading...
    Thumbnail Image
    Publication

    Challenges and opportunities of vertical FET devices using 3D circuit design layouts

    Veloso, Anabela  
    ;
    Huynh Bao, Trong
    ;
    Rosseel, Erik  
    ;
    Paraschiv, Vasile  
    ;
    Devriendt, Katia  
    Proceedings paper
    2016, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - S3S, 10/10/2016, p.1-3
  • Loading...
    Thumbnail Image
    Publication

    Challenges and progresses in high-k metal gate for Silicon-based advanced CMOS transistor architecture

    Horiguchi, Naoto  
    ;
    Ragnarsson, Lars-Ake  
    ;
    Mertens, Hans  
    ;
    Arimura, Hiroaki  
    ;
    Ritzenthaler, Romain  
    Proceedings paper
    2017, International Workshop on Dielectric Thin Films, 20/11/2017, p.102-103
  • Loading...
    Thumbnail Image
    Publication

    Challenges on surface conditioning in 3D device architectures: triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs

    Veloso, Anabela  
    ;
    Paraschiv, Vasile  
    ;
    Vecchio, Emma  
    ;
    Devriendt, Katia  
    ;
    Li, Waikin  
    ;
    Simoen, Eddy  
    Proceedings paper
    2017, 232nd ECS Fall Meeting - 15th International Symposium on Semiconductor Cleaning Science and Technology - SCST15, 1/10/2017, p.3-20
  • Loading...
    Thumbnail Image
    Publication

    Challenges on surface conditioning in 3D device architectures: triple-gate finFETs, gate-all-around lateral and vertical nanowireFETs

    Veloso, Anabela  
    ;
    Paraschiv, Vasile  
    ;
    Vecchio, Emma  
    ;
    Devriendt, Katia  
    ;
    Li, Waikin  
    ;
    Simoen, Eddy  
    Meeting abstract
    2017, 15th International Symposium on Semiconductor Cleaning Science and Technology at the 232nd ECS Fall Meeting, 1/10/2017, p.1055
  • Loading...
    Thumbnail Image
    Publication

    Comprehensive study of Ga Activation in Si, SiGe and Ge and 5 x 10-10 $Xcm2 contact resistivity achieved on Ga doped Ge using nanosecond laser activation

    Wang, Linlin
    ;
    Yu, Hao  
    ;
    Schaekers, Marc  
    ;
    Everaert, Jean-Luc
    ;
    Franquet, Alexis  
    ;
    Douhard, Bastien  
    Proceedings paper
    2017, IEEE International Electron Devices Meeting - IEDM, 2/12/2017, p.550-552
  • Loading...
    Thumbnail Image
    Publication

    Cost effective FinFET platform for stand alone DRAM 1Y and beyond memory periphery

    Spessot, Alessio  
    ;
    Sharan, Neha  
    ;
    Oh, Hyungrock  
    ;
    Ritzenthaler, Romain  
    ;
    Dentoni Litta, Eugenio  
    Proceedings paper
    2018-01, 2018 IEEE International Memory Workshop (IMW), 13/05/2018, p.1-4
  • «
  • 1 (current)
  • 2
  • 3
  • 4
  • 5
  • 6
  • »

Follow imec on

VimeoLinkedInFacebook

The repository

  • Contact us
  • Policy
  • About imec
Privacy statement | Cookie settings