Browsing by Author "Cockburn, Andrew"
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Publication A novel PEALD tunnel dielectric for three-dimensional non-volatile charge-trapping technology
Journal article2011, Electrochemical and Solid-State Letters, (14) 7, p.271-273Publication A novel PEALD tunnel dielectric for three-dimensional non-volatile charge-trapping technology
Proceedings paper2010, IEEE Semiconductor Interface Specialists Conference - SISC, 2/12/2010Publication Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
Proceedings paper2011-03, 12th International Conference on Ultimate Integration on Silicon - ULIS, 14/03/2011, p.31-33Publication Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
Journal article2012, Solid-State Electronics, 71, p.106-112Publication Composition optimization and device understanding of Si-Ge-As-Te ovonic threshold switch selector with excellent endurance
Proceedings paper2019, IEEE International Electron Devices Meeting - IEDM 2019, 7/12/2019, p.823-826Publication Cu wire resistance improvement using Mn-based self-formed barriers
Proceedings paper2014, IEEE International Interconnect Technology Conference - IITC, 20/05/2014, p.311-314Publication CVD Mn-based self-formed barrier for advanced interconnect technology
Proceedings paper2013, IEEE International Interconnect Technology Conference - IITC, 13/06/2013, p.2.3Publication CVD-Mn(Nx) as copper diffusion barrier for advanced interconnect technologies
Meeting abstract2013, 224th ECS Fall Meeting, 27/10/2013, p.2081Publication Damage reduction and sealing of low-k films by combined He and NH3 plasma treatment
Journal article2007, Electrochemical and Solid-State Letters, (10) 10, p.G76-G79Publication Demonstration of scaled 0.099μm² FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology
Proceedings paper2009-12, IEEE International Electron Devices Meeting - IEDM, 7/12/2009, p.301-304Publication Impact of barrier integrity on liner reliability in 3D through silicon vias
Proceedings paper2013, IEEE International Reliability Physics Symposium - IRPS, 14/04/2013, p.5C.5Publication Impact of LER on BEOL dielectric reliability: a quantitative model and experimental validation
Proceedings paper2009, IEEE International Interconnect Technology Conference - IITC, 1/06/2009, p.228-230Publication Implementation of Ru based barriers in 50 nm half pitch single damascene Cu/SiCOH (k=2.5) structures
; ; ; ; Proceedings paper2009, Advanced Metallization Conference 2008 (AMC2008), 23/09/2008, p.91-97Publication Implementation of Ru based barriers in 50 nm half pitch single damascene Cu/SiCOH (k=2.5) structures
; ; ; ; Meeting abstract2008, Advanced Metallization Conference - AMC, 23/09/2008Publication Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)
; ; ; ; Proceedings paper2010, IEEE International Interconnect Technology Conference - IITC, 7/06/2010Publication Integration of 50 nm half pitch single damascene copper trenches in BDII by means of double patterning 193 nm immersion lithography on metal hardmask
Oral presentation2007, Advanced Metallization Conference - AMCPublication Manufacturable processes for =32-nm-node CMOS enhancement by synchronous optimization of strain-engineered channel and external parasitic resistances
Journal article2008, IEEE Transactions on Electron Devices, (55) 5, p.1259-1264Publication Metallization of sub- 30 nm Interconnects: Comparison of different liner/seed combinations
Proceedings paper2009, Proceedings of the IEEE International Interconnect Technology Conference, 1/06/2009, p.200-202Publication Metallization options for sub- 30 nm interconnects: comparison of Cu and W metallizations
Oral presentation2010, Advanced Metallization Conference - AMCPublication Metrology for monitoring and detecting process issues in a TSV module
Journal article2014, ECS Journal of Solid State Science and Technology, (3) 6, p.Q109-Q119