Browsing by Author "Henson, Kirklen"

45nm nMOSFET with metal gate on thin SiON driving 1150μA/μm and off-state of 10nA/μm

A comparison of spike, flash, SPER and laser annealing for 45nm CMOS

A practical baseline process for advanced CMOS devices research

Advanced PMOS device architecture for highly-doped ultra-shallow junctions

Alternative gate insulator materials for future generation MOSFETs

An effective model for analysing tunneling gate leakage currents through ultrathin oxides and high-k gate stacks from Si inversion layers

An investigation of the electron tunneling leakage current through ultrathin oxides/high-k gate stacks at inversion conditions

Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime

Arsenic junction thermal stability and high-dose boron-pocket activation during SPER in nMOS transistors

Challenges in scaling of CMOS devices towards 65nm node

Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node

Channel engineering towards a full low temperature process solution for the 45 nm technology node

CMOS scaling beyond the 90 nm CMOS technology node: shallow junction and integration challenges

Demonstration of fully Ni-silicided metal gates on HfO2 based high-k gate dielectrics as a candidate for low power applications

Device characteristics of ultra-shallow junctions formed by fRTP annealing

Effects of pre-amorphization implantation (PAI) in ultra shallow junctions formed by SPER in deep sub-micron devices

Gate dielectrics for high performance and low power CMOS SoC applications

High k dielectric materials prepared by atomic layer CVD

Impact of channel engineering technology on HC performance of 100 nm MOSFETs

Implementation of high-k and metal gate materials for the 45nm node and beyond: gate patterning development