Browsing by Author "Kottantharayil, Anil"
- Results Per Page
- Sort Options
Publication A detailed experimental investigation of impact ionization in n-channel metal-oxide-semiconductor field-effect-transistors at very low drain voltages
;Kottantharayil, Anil ;Mahapatra, S.Eisele, I.Journal article2003, Solid-State Electronics, (47) 6, p.995-1001Publication A functional 41-stage ring oscillator using scaled FinFET devices with 25nm gate lengths and 10nm Fin widths applicable for the 45nm CMOS node
Journal article2004-08, IEEE Electron Device Letters, (25) 8, p.568-570Publication Analysis of the parasitic S/D resistance in multiple-gate FETs
Journal article2005, IEEE Trans. Electron Devices, (52) 6, p.1132-1140Publication Applications of Ni-based silicides to 45 nm CMOS and beyond
Proceedings paper2004, Silicon Front-End Junction Formation - Physics and Technology, 12/04/2004, p.31-42Publication CMOS integration of dual work function phase controlled Ni FUSI with simultaneous integration of nMOS (NiSi) and pMOS (Ni-rich silicide) gates on HfSiON
Proceedings paper2005-12, Technical Digest International Electron Devices Meeting - IEDM, 5/12/2005, p.661-664Publication CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach
Proceedings paper2005, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2005, p.198-199Publication Demonstration of fully Ni-silicided metal gates on HfO2 based high-k gate dielectrics as a candidate for low power applications
Proceedings paper2004-06, Technical Digest VLSI Technology Symposium, 15/06/2004, p.190-191Publication Deposition of Poly-SiGe with RTCVD
Proceedings paper2005-10, The 8th Technical and Scientific Meeting of CREMSI:FEOL from 130 to 65 nm : scaling challenges, 20/10/2005Publication Diffusion-less junctions and super halo profiles for PMOS transistors formed by SPER and FUSI gate in 45 nm physical gate length devices
Proceedings paper2004, Technical Digest International Electron Devices Meeting - IEDM, 13/12/2004, p.99-102Publication Dopant profiling in NixSi1-x gates with SIMS
Proceedings paper2005, USJ - The 8th Int. Workshop on the Fabrication, Characterization and Modeling of Ultra Shallow Junctions in Semiconductors, 5/06/2005Publication Electron-electron interaction signature peak in the substrate current versus gate voltage characteristics of N-channel silicon MOSFETS
;Kottantharayil, Anil ;Mahapatra, S.Eisele, I.Journal article2002, IEEE Trans. Electron Devices, (49) 7, p.1283-1288Publication Emerging device solutions for the post-classical CMOS era
Proceedings paper2003-04, ULSI Process Integration III, 27/04/2003, p.291-305Publication Extraction of the top and sidewall mobility in FinFETs and the impact of fin-patterning processes and gate dielectrics on mobility
Journal article2007, IEEE Trans. Electron Devices, (54) 5, p.1177-1184Publication Geometry dependence of low frequency noise in n- and p- channel MuGFETs
Proceedings paper2005, Noise and Fluctuations: 18th International Conference on Noise and Fluctuations - ICNF, 19/09/2005, p.279-282Publication GIDL (gate-induced drain leakage) and parasitic Schottky barrier leakage elimination in aggressively scaled HfO2/TiN FiNFET devices
Proceedings paper2005, Technical Digest International Electron Devices Meeting (IEDM), 5/12/2005, p.30/05/2001-30/05/2004Publication High-k dielectrics integration prospects
Proceedings paper2005, ULSI Process Integration IV, 15/05/2005, p.169-192Publication Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography
Proceedings paper2007, Symposium on VLSI Technology. Digest of Technical Papers, 14/06/2007, p.110-111Publication Influence of activation annealing and silicidation process on dopant redistribution and pile-up at the NixSiy/SiO2 interface
Proceedings paper2005-05, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 16/05/2005, p.241-248Publication Integration challenges for multi-gate devices
Proceedings paper2005, Proceedings International Conference on IC Design and Technology - ICICDT, 9/05/2005, p.187-194