Browsing by Author "Meynen, Herman"
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Publication A new ultra-low K ILD material based on organic-inorganic hybrid resins
Publication An investigation of ultra low-k dielectrics with high thermal stability for integration in memory devices
Journal article2007, Microelectronic Engineering, (84) 11, p.2582-2586Publication Aspects of metal etching for interconnect technologies
Publication Development of a global planarization process without CMP
Proceedings paper1994, 11th VLSI Multilevel Interconnect Conference - VMIC, 07/06/1994, p.172-178Publication Finite element analysis of an improved wafer level package using silicone under bump (SUB) layers
Proceedings paper2004, EuroSimE: 5th Int. Conf. on Thermal & Mechanical Simulation and Experiments in Micro-Electronics and Micro-Systems, 10/05/2004, p.163-168Publication Influence of the antireflection coating on the electromigration resistance of 0.5 µm technology metal-2 line structures
Journal article1995, Appl. Surf. Sci., 91, p.208-214Publication Integrating a hydrogen silsesquioxane spin-on dielectric in a quarter micron technology
Proceedings paper1997, 3rd International Dielectrics for ULSI Multilevel Interconnection Conference - DUMIC, 10/02/1997, p.310-316Publication Integration of the 3MS low-k CVD material in a 0.18 μm Cu single damascene process
Proceedings paper2000, Advanced Metallization Conference 1999 - AMC 1999, 28/09/1999, p.33-39Publication Integration of the 3MS low-k CVD material in a 0.18µm Cu single damascene process
Oral presentation1999, Advanced Metallization Conference; September 28-30, 1999; Orlando, FL, USA.Publication Integration of unlanded via in a non-etchback SOG direct-on-metal approach in 0.25 micron CMOS process
Proceedings paper1998, Proceedings of the IEEE 1998 International Interconnect Technology Conference - IITC, 1/06/1998, p.45-47Publication Integration of unlanded via in a non-etchback SOG direct-on-metal approach in 0.25 micron CMOS process
Oral presentation1998, Advanced Metallization ConferencePublication Interlevel dielectric engineering for improved device performance in half-micron CMOS
Proceedings paper1994, 11th VLSI Multilevel Interconnect Conference - VMIC, 07/06/1994, p.111-113Publication Low-k materials etch and strip optimization for sub 0.25µm technology
Proceedings paper1999, Proceedings of the International Interconnect Technology Conference - IITC; San Francisco, CA, USA., p.53-55Publication Low-k organic spin-on materials in a non-etchback interconnect strategy
Proceedings paper1996, 2nd International Dielectrics for VLSI/ULSI Multilevel Interconnection Conference - DUMIC, 20/02/1996, p.52-59Publication Minimizing within die non uniformity in CMP by optimising polishing parameters and consumables
Proceedings paper1997, Advanced Metallization and Interconnect Systems for ULSI Applications in 1996, 1/10/1996, p.525-530Publication Optimization of etching and stripping chemistries for Z3MS TM low-k
Proceedings paper2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference ; 4-6 June 2001; Burlingame, CA, USA., p.174-176Publication Patternable silicones for next generation packaging reliability requirements
Publication Photopatternable silicone compositions for electronics packaging applications
Publication Physical and electrical characterization of silsesquioxane-based ultra-low k dielectric films
Publication Process optimization and integration of trimethylsilane deposited a-SiC:H and SiOC:H dielectric thin films for damascene processing
Oral presentation2000, MRS Spring Meeting 2000. Symposium D: Materials, Technology, and Reliability for Advanced Interconnects and Low-k Dielectrics; 2