Browsing by Author "Peng, Lan"
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Publication 3D integration technology using W2W direct bonding and TSV
Proceedings paper2015, Electronics Packaging Technology Conference - EPTC, 2/12/2015Publication 3D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
; ; ; ; ; Journal article2018-11, IEEE Transactions on Electron Devices, (65) 11, p.5165-5171Publication 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
; ; ; ; ; Proceedings paper2018, IEEE Symposium on VLSI Technology, 18/06/2018, p.69-70Publication 3D-SoC integration utilizing high accuracy wafer level bonding
Proceedings paper2016, IEEE 18th Electronics Packaging Technology Conference - EPTC, 30/11/2016, p.111-114Publication A novel integration scheme for wafer singulation and selective processing using temporary dry film resist
Proceedings paper2021, IEEE 71st Electronic Components and Technology Conference (ECTC), JUN 01-JUL 04, 2021, p.793-796Publication Advances in SiCN-SiCN bonding with high accuracy wafer-to-wafer (W2W) stacking technology
Proceedings paper2018, IEEE International Interconnect Technology Conference - IITC, 4/06/2018, p.985-992Publication Bonding yield analysis of enclosed structures
Meeting abstract2018, AiMES Meeting, 30/09/2018, p.945Publication Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
Proceedings paper2019, 2019 Symposia on VLSI Technology and Circuits, 9/06/2019, p.T56-T57Publication Characterization and benchmarking of the low inter-tier thermal resistance of 3D hybrid Cu/dielectric wafer-to-wafer bonding
Journal article2017-03, Journal of Electronic Packaging, (139) 1, p.11008-011008-9Publication Characterization of bonding activation sequences to enable ultra-low Cu/SiCN wafer level hybrid bonding
Publication Characterization of extreme Si thinning proces for wafer-to-wafer stacking
Proceedings paper2016, IEEE 66th Electronic Components and Technology Conference - ECTC, 31/05/2016, p.2095-2102Publication Characterization of inorganic dielectric layers for low thermal budget wafer to wafer bonding
Proceedings paper2017, 5th International Workshop on Low Temperature Bonding for 3D Integration - LTB-3D, 16/05/2017, p.24Publication Copper oxide direct bonding of 200 mm CMOS wafers with five metal levels and TSVs: morphological and electrical characterization
; ; ; ; Guerrieri, StefanoProceedings paper2016, Processing Materials of 3D Interconnects, Damascene and Electronics Packaging 8, 2/10/2016, p.43-46Publication Copper oxide direct bonding of 200mm CMOS wafers: morphological and electrical characterization
Proceedings paper2015, IMAPS 48th Annual international symposium on Microelectronics, 26/10/2015, p.594-597Publication Defect identification in bonding surface layer by positron annihilation spectroscopy
Proceedings paper2019, 2019 6th International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D 2019), 21/05/2019Publication Development of multi-stack dielectric wafer bonding
Proceedings paper2016, 17th International Conference on Electronic Packaging Technology - ICEPT, 16/08/2016, p.22-25Publication Development of wafer-level adhesive bonding for fine-pitch 3-D connections
; ; ; ; ; Meeting abstract2017, The International Conference on Wafer Bonding - Waferbond, 27/10/2017Publication Direct bonding of low temperature heterogeneous dielectrics
; ; ; ; ; Proceedings paper2019, 69th IEEE Electronic Components and Technology Conference (ECTC), MAY 29-31, 2019, p.2206-2212Publication Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration
Proceedings paper2017, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference - IEEE S3S, 16/10/2017, p.5.3
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