Browsing by Author "Rohr, Erika"
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Publication 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.181-182Publication A Dy2O3-capped HfO2 dielectric and TaCx-based metals enabling low-Vt single-metal-single-dielectric gate stack
Proceedings paper2007, Technical Digest International Electron Devices Meeting - IEDM, 10/12/2007, p.535-538Publication ALD deposition of high-k and metal gate stacks for advanced CMOS applications
Proceedings paper2004, Atomic Layer Deposition Conference, 16/08/2004Publication Band edge work function metal gates using PEALD TaCN electrodes
Oral presentation2009, 9th International Conference on Atomic Layer Deposition - ALDPublication Challenges with respect to high-k/metal gate stack etching and cleaning
Proceedings paper2007, Physics and Technology of High-k Dielectrics, 7/10/2007, p.275-283Publication Cleaning and strip requirement for metal gate based CMOS integration
; ; ; ; Publication Cleaning and strip requirements for metal gate based CMOS integration
; ; ; ; Publication Dual-channel technology with Cap-free single metal gate for high performance CMOS in gate-first and gate-last integration
Proceedings paper2011, IEEE International Electron Devices Meeting - IEDM, 5/12/2011, p.654-657Publication Effective metal gate work function modification by ion implantation with W-based gate stack
Oral presentation2008, 5th International Symposium on Advanced Gate Stack TechnologyPublication Effectiveness of nitridation of hafnium silicate dielectrics: a comparison between thermal and plasma nitridation
Journal article2007, IEEE Trans. Electron Devices, (54) 7, p.1771-1775Publication Electrical and physical characterization of MOSFETs with MBE grown La2HfO7 and HfO2 high-k dielectrics integrated in a conventional flow
Oral presentation2005, Workshop "Nouveaux Oxides à Forte Permittivité dans l'Intégration des Semiconducteurs"Publication Gate-last vs. gate-first technology for aggressively scaled EOT Logic/RF CMOS
Proceedings paper2011, Symposium on VLSI Technology, 13/06/2011, p.34-35Publication High performance Si.45Ge.55 implant free quantum well FET featuring low temperature process, eSiGe stressor and transversal strain relaxation
Proceedings paper2011, IEEE International Electron Devices Meeting - IEDM, 5/12/2011, p.829-832Publication High-k gate stack engineering – towards meeting low standby power and high performance targets
; ; ; ; Proceedings paper2005, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 15/05/2005, p.109-117Publication Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance
Proceedings paper2010, IEEE Symposium on VLSI Technology, 15/06/2010, p.109-110Publication Integration of high-K gate dielectrics - wet etch, cleaning and surface conditioning
Proceedings paper2004, Cleaning Technology in Semiconducting Device Manufacturing VIII. Proceedings of the International Symposium, 13/10/2003, p.67-77Publication Integration of PVD ruthenium as a pMOS metal gate in scaled planar devices: workfunction and electrical performance on HfO2
Proceedings paper2005, 4th International Conference on Semiconductor Technology - ISTC, 14/03/2005, p.62-71Publication Low VT CMOS using doped Hf-based oxides, TaC-based metals and laser-only anneal
Proceedings paper2007, Technical Digest International Electron Devices Meeting - IEDM, 10/12/2007, p.49-52Publication Low VT metal-gate/high-k nMOSFETs - PBTI dependence and VT tune-ability on La/Dy-capping layer locations and laser annealing conditions
Publication Low-frequency noise analysis of the impact of an LaO cap layer in HfSiON/Ta2C gate stack nMOSFETs
Meeting abstract2009, 216th ECS Meeting, 4/10/2009, p.2370
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