Browsing by Author "Singanamalla, Raghunath"

A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM

Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

Achieving low-VT Ni-FUSI CMOS via Lanthanide incorporation in the gate stack

Demonstration of metal-gated low Vt n-MOSFETs using a Poly-Si/TaN/Dy2O3/SiON gate stack with a scaled EOT value

Demonstration of Ni fully GermanoSilicide as a pFET gate electrode candidate on HfSiON

Demonstration of phase-controlled Ni-FUSI CMOSFETs employing SiON dielectrics capped with sub-monolayer ALD HfSiON for low power applications

Effect of degas before metal gate deposition on the threshold voltage

Effective metal gate work function modification by ion implantation with W-based gate stack

Effective work-function modulation by aluminum-ion implantation for metal-gate technology (poly-Si/TiN/SiO2)

Electrical properties of n-MOSFETs using the NiSi:Yb FUSI electrode

Gate-dielectric interface effects in low frequency (1/f) noise in p-MOSFETs with high-K dielectrics

Investigation of high-k-metal gate integration for sub 45 nm planar bulk CMOS technologies

Low VT CMOS using doped Hf-based oxides, TaC-based metals and laser-only anneal

Low Vt Ni-FUSI CMOS technology using a DyO cap layer with either single or dual Ni-phases

Metal inserted poly-Si (MIPS) and FUSI dual metal (TaN and NiSi) CMOS integration

Methodology for flatband voltage measurement in fully depleted floating-body FinFETs

N-type VT tuning by Te ion implantation in moly-based metal gates with high-k dielectric for fully depleted devices

Nitrogen profile and dielectric cap layer (Al2O3, Dy2O3, La2O3) engineering on Hf-silicate

Performance enhancement of Poly-Si/TiN/SiON based pMOSFETs by addition of an AlO capping layer

Single-wafer wet chemical oxide formation for pre-ALD high-k deposition on 300 mm wafer