Browsing by Author "Travaly, Youssef"
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Publication 300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications
Meeting abstract2010-11, IEEE International 3D System Integration Conference - 3DIC, 16/11/2010Publication 3D stacked IC demonstrator using hybrid collective die-to-wafer bonding with copper through silicon vias (TSV)
; ;Coenen, Jens; ; ; Proceedings paper2009, IEEE 3D-IC, 28/09/2009Publication 3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding
Proceedings paper2009, IEEE International Electron Devices Meeting - IEDM, 7/12/2009, p.357-360Publication 3D technology roadmap and status
Proceedings paper2011, IEEE International Interconnect Technology Conference and Materials for Advanced Metallization - IITC/MAM, 8/05/2011Publication 3D wafer-level packaging die stacking using spin-on-dielectric polymer liner through-silicon vias
Journal article2011, IEEE Transactions on Components, Packaging and Manufacturing Technology, (1) 6, p.833-840Publication A high-reliable Cu/ULK integration scheme using Metal Hard Mask and Low-k capping film
Oral presentation2007, Advanced Metallization Conference: 17th Asian SessionPublication A theoretical and experimental study of atomic-layer-deposited films onto porous dielectric substrates
Journal article2005-10, Journal of Applied Physics, (98) 8, p.083515-1-083515-9Publication Aggressive scaling of Cu lowk: impact on metrology
Proceedings paper2005, Characterization and Metrology for ULSI Technology, 14/03/2005, p.475-481Publication Air-gap formation by UV-assisted decomposition of CVD material
Meeting abstract2008, 17th Workshop Materials for Advanced Metallization, 2/03/2008Publication Air-gap formation by UV-assisted decomposition of CVD material
Journal article2008, Microelectronic Engineering, (85) 10, p.2071-2074Publication Atomic layer deposited barriers for copper interconnects
Meeting abstract2004, AVS 51 International Symposium, 14/11/2004, p.TF-MoM1Publication Bottom-up engineering of subnanometer copper diffusion barriers using NH2-derived self assembled monolayers
Journal article2010, Advanced Functional Materials, (20) 7, p.1125-1131Publication Challenges for structural stability of ultra-low-k based interconnects
Journal article2004, Microelectronic Engineering, (75) 1, p.54-62Publication Challenges in the implentation of low-k dielectrics in the back-end of line
Journal article2005, Microelectronic Engineering, 80, p.337-344Publication Characterization and optimization of Cu-low k for 45nm and beyond
Proceedings paper2004, Proceedings 3rd Hiroshima International Workshop on Nanoelectronics for Tera-Bit Information Processing, 6/12/2004, p.10-18Publication Characterization and optimization of porogen based PECVD deposited extreme low-k materials as a function of UV-cure time
Journal article2007, Surface and Coatings Technology, (201) 22_23, p.9264-9268Publication Characterization of atomic layer deposited nanoscale structure on dense dielectric substrates by X-ray reflectivity
;Travaly, Youssef ;Schuhmacher, J. ;Martin Hoyas, Ana ;Abell, T. ;Sutcliffe, VicJonas, M.Journal article2005, Microelectronic Engineering, (82) 3_4, p.639-644Publication Characterization of PVD TaN and ALD WNxCy copper diffusion barriers on a porous CVD low-k material
Proceedings paper2004, Advanced Metallization Conference 2003, 21/10/2003, p.723-728Publication Characterization of the growth of atomic layer deposited WNxCy films on various substrates
;Martin Hoyas, Ana ;Travaly, Youssef ;Schuhmacher, Jorg ;Sajavaara, TimoWhelan, CarolineOral presentation2005, AVS 2005Publication Cleaning requirement in the thinning module for 3D-Stacked IC (3D-SIC) integration
Meeting abstract2010, 10th International Symposium on Ultra-Clean Processing of Semiconductor Devices - UCPSS, 19/09/2010, p.188-189