Browsing by author "Guo, Wei"
Now showing items 1-20 of 22
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3D chip package interaction thermo-mechanical challenges: proximity effects of through silicon vias and μ-bumps
Guo, Wei; Van der Plas, Geert; Ivankovic, Andrej; Eneman, Geert; Cherman, Vladimir; De Wachter, Bart; Mercha, Abdelkarim; Gonzalez, Mario; Civale, Yann; Redolfi, Augusto; Buisson, Thibault; Jourdain, Anne; Vandevelde, Bart; Rebibis, Kenneth June; De Wolf, Ingrid; La Manna, Antonio; Beyer, Gerald; Beyne, Eric; Swinnen, Bart (2012) -
3D stacking induced mechanical stress effects
Cherman, Vladimir; Van der Plas, Geert; De Vos, Joeri; Ivankovic, Andrej; Lofrano, Melina; Simons, Veerle; Gonzalez, Mario; Vanstreels, Kris; Wang, Teng; Daily, Robert; Guo, Wei; Beyer, Gerald; La Manna, Antonio; De Wolf, Ingrid; Beyne, Eric (2014) -
Analysis of copper plasticity impact in TSV-middle and backside TSV-last fabrication processes
Guo, Wei; Karmarkar, Aditya; Xu, Xiaopeng; Van der Plas, Geert; Van Huylenbroeck, Stefaan; Gonzalez, Mario; Absil, Philippe; El Sayed, Karim; Beyne, Eric (2015) -
Chip package interaction: A stress analysis on 3D IC's packages
Lofrano, Melina; Gonzalez, Mario; Guo, Wei; Van der Plas, Geert (2015) -
Chip-package interaction
De Wolf, Ingrid; Vandevelde, Bart; Debecker, Bjorn; Ivankovic, Andrej; Vanstreels, Kris; Gonzalez, Mario; Lofrano, Melina; Guo, Wei; Cherman, Vladimir (2013) -
Chip-package interaction in 3D stacked IC packages using finite element modelling
Vandevelde, Bart; Ivankovic, Andrej; Debecker, Bjorn; Lofrano, Melina; Vanstreels, Kris; Guo, Wei; Cherman, Vladimir; Gonzalez, Mario; Van der Plas, Geert; De Wolf, Ingrid; Beyne, Eric; Tokei, Zsolt (2014) -
Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology
Guo, Wei; Moroz, Victor; Van der Plas, Geert; Choi, M.; Redolfi, Augusto; Smith, L.; Eneman, Geert; Van Huylenbroeck, Stefaan; Su, P.D.; Ivankovic, Andrej; De Wachter, Bart; Debusschere, Ingrid; Croes, Kris; De Wolf, Ingrid; Mercha, Abdelkarim; Beyer, Gerald; Swinnen, Bart; Beyne, Eric (2013) -
Cu TSV stress: avoiding Cu protrusion and impact on devices
Beyne, Eric; De Messemaeker, Joke; Guo, Wei (2014) -
IC-package interaction
Vandevelde, Bart; Ivankovic, Andrej; Debecker, Bjorn; Lofrano, Melina; Vanstreels, Kris; Guo, Wei; Cherman, Vladimir; Gonzalez, Mario; Van der Plas, Geert; De Wolf, Ingrid; Beyne, Eric; Tokei, Zsolt (2013) -
Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime
Guo, Wei; Choi, Munkang; Rouhi Najaf Abadi, Alireza; Moroz, Victor; Van der Plas, Geert; Absil, Philippe; Beyne, Eric (2014) -
Impact of strain and source/drain engineering on the low-frequency noise behaviour in n-channel Tri-Gate FinFETs
Guo, Wei; Cretu, B.; Routoure, J.-M.; Carin, R.; Simoen, Eddy; Mercha, Abdelkarim; Collaert, Nadine; Put, Sofie; Claeys, Cor (2008) -
Impact of through silicon via induced mechanical stress on fully depleted bulk FinFET technology
Guo, Wei; Van der Plas, Geert; Ivankovic, Andrej; Cherman, Vladimir; Eneman, Geert; De Wachter, Bart; Togo, Mitsuhiro; Redolfi, Augusto; Kubicek, Stefan; Civale, Yann; Chiarella, Thomas; Vandevelde, Bart; Croes, Kristof; De Wolf, Ingrid; Debusschere, Ingrid; Mercha, Abdelkarim; Thean, Aaron; Beyer, Gerald; Swinnen, Bart; Beyne, Eric (2012) -
Impact of wafer thinning on front-end reliability for 3D integration
Vaisman Chasin, Adrian; Scholz, Mirko; Guo, Wei; Franco, Jacopo; Potoms, Goedele; Jourdain, Anne; Linten, Dimitri; Van der Plas, Geert; Absil, Philippe; Beyne, Eric (2016) -
Low-frequency noise assessment of silicon passivated Ge pMOSFETs with TiN/TaN/HfO2 gate stack
Guo, Wei; Nicholas, Gareth; Kaczer, Ben; Todi, Ravi; De Jaeger, Brice; Claeys, Cor; Mercha, Abdelkarim; Simoen, Eddy; Cretu, B.; Routoure, J.M.; Carin, R. (2007) -
Modeling copper plastic deformation and liner viscoelastic flow effects on performance and reliability in Through Silicon Via (TSV) fabrication processes
Karmarkar, A.P.; Xu, X.; El Sayed, K.; Guo, Wei; Van der Plas, Geert; Van Huylenbroeck, Stefaan; Gonzalez, Mario; Absil, Philippe; Beyne, Eric (2019) -
Noise coupling between TSVs and active devices: planar nMOSFETs vs. nFinFETs
Sun, Xiao; Rouhi Najaf Abadi, Alireza; Guo, Wei; Bel Ali, K.; Rack, M.; Roda Neve, Cesar; Choi, M.; Moroz, V.; De Wolf, Ingrid; Raskin, J.P.; Van der Plas, Geert; Beyne, Eric; Absil, Philippe (2015) -
Performance and reliability impact of copper plasticity in backside TSV-last fabrication process
Karmarkar, Aditya P.; Guo, Wei; Xu, Xiaopeng; Van der Plas, Geert; Van Huylenbroeck, Stefaan; Gonzalez, Mario; Absil, Philippe; El Sayed, Karim; Beyne, Eric (2016) -
Reliability challenges related to TSV integration and 3D stacking
Croes, Kristof; De Messemaeker, Joke; Li, Yunlong; Guo, Wei; Varela Pedreira, Olalla; Cherman, Vladimir; Stucchi, Michele; De Wolf, Ingrid; Beyne, Eric (2016) -
Study of 3D process impact on advanced CMOS devices
La Manna, Antonio; Guo, Wei; Van Huylenbroeck, Stefaan; Sirignano, Emilio; Cherman, Vladimir; Van der Plas, Geert; De Wachter, Bart; Phommahaxay, Alain; Jourdain, Anne; Beyer, Gerald; Beyne, Eric (2013) -
Through silicon via to FinFET noise coupling in 3-D integrated circuits
Rouhi Najaf Abadi, Alireza; Guo, Wei; Sun, Xiao; Ben Ali, K.; Raskin, J.P; Rack, M.; Roda Neve, Cesar; Choi, M.; Moroz, V.; Van der Plas, Geert; De Wolf, Ingrid; Beyne, Eric; Absil, Philippe (2015)