Browsing by Author "Chew, Soon Aik"

3D simulation for melt laser anneal integration in FinFET's contact

A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions

A low-power HKMG CMOS platform compatible with DRAM node 2x and beyond

A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies

Al-induced defect generation in cubic phase HfO2/SiO2/Si gate stacks

Application of selective epitaxial growth for merging fins in source/drain areas of sub 20 nm FinFET transistors

Application of selective epitaxial growth for merging fins in source/drain areas of sub 20 nm FinFET transistors

Co and Ru dual damascene compatible metallization studies

Cu Pad Surface Height Evaluation Technique by In-line SEM for Wafer Hybrid Bonding

Diffusion and gate replacement: a new gate-first high-k/metal gate CMOS integration scheme suppressing gate height symmetry

Dummy design characterization for STI CMP with fixed abrasive

Effective work function engineering for aggressively scaled planar and FinFET-based devices with high-k last replacement metal gate technology

Effective work function engineering for aggressively scaled planar and multi-gate fin field-effect transistor-based devices with high-k last replacement metal gate technology

Electrical characteristics of P-type bulk Si fin field-effect transistor using solid-source doping with 1-nm phosphosilicate glass

Exploring Bonding Mechanism of SiCN for Hybrid Bonding

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

Gate-all-around transistors based on vertically stacked Si nanowires

Heterostructure at CMOS source/drain: contributor or alleviator to the high access resistance problem?

High-throughput in-line SEM Metrology for Cu Pad Nanotopography for Hybrid Bonding Applications

Highly scalable bulk FinFET devices with multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond